Arm SystemC Cycle Models

Getting Started

Arm SystemC Cycle Models simplify virtual prototype creation. Models that are IEEE std. 1666-2011-compliant allow you to rapidly assemble systems and integrate other Accellera SystemC and Transaction Level Modeling (TLM) component models to create accurate virtual prototypes.

Because models are the key to creating a virtual prototype, Arm supports a wide range of models in a variety of formats including:

• Flexible SystemC model support for easy creation and integration

• High performance cycle-accurate and implementation-accurate models compiled by Cycle Model Studio

• Verilog and VHDL co-simulation with leading RTL Simulators

Platform Debug

Assembling system models is only part of the solution: the key lies in the ability to execute the prototype, examine the behavior of the system, and analyze key metrics. Arm Cycle Models provide debug interfaces tailored for both hardware and software engineers. You have full visibility and execution control of your design. Software engineers are able to view code, control the simulation at clock edge granularity, and examine registers and memories. Hardware engineers can examine signals, dump waveforms, and trace execution through the system. Run-time performance profiling gives you immediate feedback on system behavior during execution.

Architectural Analysis

Development and analysis of system architecture requires the accuracy to model key system characteristics, especially with complex bus architectures and multi-core communications models. Arm Cycle Models provide the accuracy, performance, and flexibility to model complex systems and perform the analysis required to make critical design decisions. Instead of ad-hoc model approximations and paper-and-pencil calculations, architects can now prove their design assumptions before committing to the design implementation. The unique benefits for architectural analysis enable first-turn success of your SoC:

• Create cycle-accurate system models required for detailed architectural analysis and explore the performance impact of hardware/software trade-offs

• Measure interconnect performance of complex bus architectures using actual system behavior to drive traffic

• Quickly and easily make changes and explore design space alternatives before committing to an implementation

Hardware and Software System Validation

System validation requires the ability to model the entire system working together, and provide accurate models of both the hardware and software. Cycle-accurate virtual prototypes provide a way to develop and validate software before committing to physical hardware implementations. Effective driver and firmware development requires the detail and performance that is provided by Arm. The benefits for hardware/software system validation provide insight:

• Speed system integration time by debugging your software on virtual platforms before physical prototypes are available

• Reduce risk by validating hardware implementations using actual system software

• Eliminate hardware physical prototype availability as a bottleneck to software development

• Accelerate the process of debugging, implementing hardware or software changes, and then re-executing the system.

Accurate Models from Arm IP Exchange

Arm Cycle Model solutions leverage models from Arm IP Exchange. This web portal enables around the clock access to Arm IP. Models can be easily configured, built, downloaded, and managed, then integrated directly into a SystemC system. The benefits of Arm IP Exchange are numerous:

• Configuration — IP Exchange understands the valid configuration options for each piece of Arm IP and only permits compatible combinations of these options to be chosen. 

• Quality — Models are generated in a "clean" environment that is proven and continually regression tested. Arm IP Exchange understands the dependencies between the model and SystemC to ensure compatibility.

• Usability — Models are configured using a short series of questions, which automatically adapt as answers are given, to ensure that only valid configurations are built. No RTL or design knowledge is required to configure or build a model.

• Enhanced Satisfaction — Arm IP Exchange is available 24/7 allowing you to configure the model as and when you need it. You can easily check on the status of any model you requested to be automatically built.

• IP Management — Arm IP Exchange maintains a secure history of user models and automatically issues a notification when a new revision or model is available. This secure history mechanism enables you to leverage IP and configurations that are used elsewhere within your organization.