Sample Arm Cortex-A53 CPAK
Sample Arm Cortex-A53 CPAK

Getting Started

Virtual prototypes play a vital role in the design and analysis of system on chip designs. In order to maximize the time spent being productive with virtual prototypes and minimize the time required to create them, Arm supplies a rich library of Cycle Performance Analysis Kits (CPAKs). These extensible virtual prototypes come complete with models, system information and software to enable designer productivity within minutes of download.


Access CPAKs 


CPAK Features

  • Pre-built virtual prototypes featuring advanced technology such as the Arm Cortex-A72Cortex-A57, Cortex-R8 and Cortex-M7 processors
  • 100% accurate models for critical performance elements including processors, fabric, memory controllers and GPUs
  • Arm Fast Model representations to enable application software development at millions of instructions per second
  • Swap & Play, to enable the Arm Fast Model representation to switch to 100% accuracy at any software break-point
  • Bare-metal software package to initialize components and enable easy customization and benchmarking
  • Linux OS packages including source code 

Simple Customization

CPAKs are designed to be useful immediately after download, but not all SoCs are the same. To better model the behavior of your actual SoC, CPAKs can also be easily customized using SoC Designer. SoC Designer enables IP blocks to be reconfigured or replaced. Additional blocks and subsystems can also be added to the system. Designers are able to take advantage of the complete Arm model ecosystem including models from Arm IP Exchange, models compiled from RTL using Cycle Model Studio or handwritten models in C/C++ or SystemC.

Source code is also provided for all software components to enable easy customization. CPAKs minimize the setup tasks typically associated with SoC design and enable engineers to focus their efforts in more productive areas.

Architectural Analysis

CPAKs are ideally suited for accurate architectural analysis. They contain 100% accurate models compiled directly from RTL and instrumented for interactive design, debug and analysis. CPAKs let you see the behavior of the actual silicon months before it is built. This enables the designer to make architectural decisions with confidence. CPAKs take advantage of all of SoC Designer's architectural analysis and visualizations tools to give the designer unmatched insight into actual SoC behavior.

System Performance Optimization

Although many benchmarks execute on a bare-metal system, a large number of them require an OS to be present. Traditionally this presents a problem because the cycle accurate models which are so beneficial for bare metal benchmarks and optimization are simply too slow to be used with an OS. Even booting an OS on a platform containing only cycle accurate models can take days.

CPAKs for the Linux and Android OS solve this problem by using Arm's Swap & Play technology. This enables the OS to boot in seconds and get to the software area of interest for performance analysis. The system representation is then swapped to be 100% accurate (for all or just part of the system) and execution continues. This technique enables accurate benchmarking and optimizations.

Unmatched IP Integration

Your SoC design doesn't just use IP from a single vendor. Your virtual prototype representation shouldn't either. CPAKs can easily accommodate additional third party IP models. These models can either be added to the CPAK platform or used to replace a delivered component. Future CPAKs will also include select third party IP to further accelerate the integration process.

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Answered Where do I find presentations and photos from SC'18? 1 votes 975 views 0 replies Started 6 months ago by John Linford Answer this
Not answered What options do I have for a GUI and an LCD? 0 votes 17 views 0 replies Started 9 hours ago by AmyTheBUn Answer this
Answered Mali Offline compiler GLSL clamp performance on Mali-Gxx 0 votes 90 views 3 replies Latest 11 hours ago by Peter Harris Answer this
Answered how to calculate unaligned address for APB? 0 votes 229 views 5 replies Latest 11 hours ago by Colin Campbell Answer this
Not answered How to get the required FLOPs for my neural network
  • Deep Learning
0 votes 25 views 0 replies Started 12 hours ago by fset89 Answer this
Suggested answer Relocating the Vector table in Cortex - M0 0 votes 45 views 1 replies Latest 13 hours ago by 42Bastian Schick Answer this
Not answered FVP License
  • AEMv8 FVP
0 votes 23 views 0 replies Started 14 hours ago by Bill M Answer this
Answered why PSTRB signal in APB4 have four bits?
  • APB
  • AMBA
  • AMBA 4
0 votes 1108 views 4 replies Latest 15 hours ago by Colin Campbell Answer this
Discussion 4-kbyte boundary space 0 votes 9697 views 10 replies Latest 15 hours ago by Colin Campbell Answer this
Suggested answer Timer0 do not count at the theoretical frequency 0 votes 38 views 1 replies Latest 15 hours ago by 42Bastian Schick Answer this
Answered Mali Graphics Debugger Memory statistics
  • Mali Graphics Debugger
0 votes 264 views 3 replies Latest 17 hours ago by Peter Harris Answer this
Answered Disable data prefetching in a Cortex-A53 running Android
  • Cortex-A53
  • el1
  • l1
  • l2
0 votes 166 views 3 replies Latest 17 hours ago by vstehle Answer this
Answered Where do I find presentations and photos from SC'18? Started 6 months ago by John Linford 0 replies 975 views
Not answered What options do I have for a GUI and an LCD? Started 9 hours ago by AmyTheBUn 0 replies 17 views
Answered Mali Offline compiler GLSL clamp performance on Mali-Gxx Latest 11 hours ago by Peter Harris 3 replies 90 views
Answered how to calculate unaligned address for APB? Latest 11 hours ago by Colin Campbell 5 replies 229 views
Not answered How to get the required FLOPs for my neural network Started 12 hours ago by fset89 0 replies 25 views
Suggested answer Relocating the Vector table in Cortex - M0 Latest 13 hours ago by 42Bastian Schick 1 replies 45 views
Not answered FVP License Started 14 hours ago by Bill M 0 replies 23 views
Answered why PSTRB signal in APB4 have four bits? Latest 15 hours ago by Colin Campbell 4 replies 1108 views
Discussion 4-kbyte boundary space Latest 15 hours ago by Colin Campbell 10 replies 9697 views
Suggested answer Timer0 do not count at the theoretical frequency Latest 15 hours ago by 42Bastian Schick 1 replies 38 views
Answered Mali Graphics Debugger Memory statistics Latest 17 hours ago by Peter Harris 3 replies 264 views
Answered Disable data prefetching in a Cortex-A53 running Android Latest 17 hours ago by vstehle 3 replies 166 views