Getting Started

Fast Models are accurate, flexible programmer's view models of Arm IP, allowing you to develop software such as drivers, firmware, OS and applications prior to silicon availability. They allow full control over the simulation, including profiling, debug and trace. Fast Models can be exported to SystemC and TLM 2.0, allowing integration into the wider SoC design process.

 

What's new in 11.6?

  • Fast Models and example platforms for the Neoverse-E1 and Neoverse-N1 processors
  • Support for Armv8.5-A at Release quality
  • Support for Armv8.1-M at Release quality. Includes support for the Helium vector extensions (through an add-on package)
  • Support for building platforms with Visual Studio 2017 on Windows 10 at Alpha quality
A bug, A chip, a robot etc.

Components in a Virtual Prototype

A complete virtual prototype of a system contains more than just an Instruction Set Simulator. A full system consists of:

  • Fast, accurate models of cores, subsystems or systems
  • SystemC interface for integration with EDA tools and other IP blocks
  • APIs for debug (CADI) and trace (MTI), allowing full control and an interface to DS-5, MDK and 3rd party debug tools
  • Python based scripting for runtime control, checking and reporting
  • Visualization, file system access, peripherals and networking from virtual I/O
  • Fully compatible Linaro software stacks, from boot code to Linux and Android OS support

Software Development with Fast Models

Complete & Accurate

Fast Models are available for all Cortex processors, CCI and CCN interconnect, as well as other system IP. Fast Models are functionally accurate, so banked and co-processor registers, exception levels, translation tables and cache coherency are all available to programmers.

Hybrid Simulation

Connect a CPU subsystem to peripherals on hardware emulators via AMBA transactors for emulation acceleration. Compatible with Cadence, Mentor Graphics and Synopsys emulators for maximum flexibility in your software development and IP validation process.

Save and Restore

Checkpointing allows you to save your simulation once the OS has booted, so that you can restart from there and jump quickly back into your software. For regression testing, multiple simulations can be restarted from a single checkpoint.

Timing Annotation

Fast Models interact with TLM approximately timed models for high level software performance estimation. This helps to give an idea of how software will perform on the real device, saving software development time further into the project.

Fast Models Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Fast Models.

CPU Fast Models

CPU Family Processor
Neoverse Neoverse-E1 new, Neoverse-N1 new
Cortex-A Series Cortex-A32, Cortex-A35, Cortex-A53, Cortex-A55, Cortex-A57, Cortex-A72, Cortex-A73, Cortex-A75, Cortex-A76, Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A15, Cortex-A17
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R4, Cortex-R5, Cortex-R7
Cortex-M Series Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4, Cortex-M7

Fixed Virtual Platform Downloads

Fixed versions of Fast Models are also available, giving software developers a ready-to-use model of a complete Arm system. They can be downloaded, licensed individually and imported into DS-5 for ease of use. Fixed Virtual Platforms are a convenient way of testing software without needing to wait for development boards to become available.

Learn more


System IP Fast Models

System IP Family
Interconnect CCI-400, CCI-500, CCI-550, CCN-502, CCN-504, CCN-508, CCN-512, CMN-600
Interrupt Controllers GIC-400, GIC-500, GIC-600
System Memory Management Units MMU-400, MMU-500, MMU-600
Other DMC-620, DMC-500, DMC-520, DMC-400, DMA-330, TZC-400 

Peripherals and Infrastructure

Type Variant
Interfaces Ethernet, MMC, CLDC, HDLCD, VirtIO Block, Virtio Plan, VFS
Peripheral UART, MMU, Mouse and Keyboard, SSP, Timers, Clocks, GPIO
Memories RAM, Flash, NAND Flash, PL080, PL340, PL350, L2C-310
TrustZone TZIC, TZMA, TZPC
Other Visualization, Bridges to AMBA-PV, PV Bus, File/App Loaders

Media IP Fast Models

Media IP
 
Mali Display Processors
Mali-DP500, Mali-DP550, Mali-DP650, Mali-D71
Mali Video Processors
Mali-V550, Mali-V61
Mali GPU
Mali-G51, Mali-G71, Mali-G72, Mali-G76, Generic Graphics Accelerator (GGA)

 

Architectural Fast Models

  Available Models
CPU
Armv8-A (up to version 8.5)
Armv8-M (up to version 8.1)
Interrupt Controller
GICv2, GICv3, GICv4
SMMU SMMUv3


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Community Blogs

Community Forums

Not answered How to defined board.txt to STM32YYXX Series?
  • Microcontroller
0 votes 36 views 0 replies Started 2 days ago by @chu!! Answer this
Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+
  • CoreLink MMU-500 System Memory Management Unit
  • Armv8-A
  • SMMUv2
0 votes 45 views 0 replies Started 4 days ago by Ciro Donnarumma Answer this
Suggested answer boundary concept
  • AMBA
  • AXI
  • AHB
0 votes 349 views 3 replies Latest 6 days ago by harrykayn Answer this
Suggested answer State Machine for AHB-Lite Protocol
  • ahb-lite
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0 votes 220 views 3 replies Latest 8 days ago by Colin Campbell Answer this
Suggested answer Amba Adaptive Traffic Profiles question
  • AMBA
0 votes 141 views 1 replies Latest 11 days ago by Matteo Maria Andreozzi Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
0 votes 221 views 2 replies Latest 12 days ago by Zax Answer this
Not answered How to defined board.txt to STM32YYXX Series? Started 2 days ago by @chu!! 0 replies 36 views
Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+ Started 4 days ago by Ciro Donnarumma 0 replies 45 views
Suggested answer boundary concept Latest 6 days ago by harrykayn 3 replies 349 views
Suggested answer State Machine for AHB-Lite Protocol Latest 8 days ago by Colin Campbell 3 replies 220 views
Suggested answer Amba Adaptive Traffic Profiles question Latest 11 days ago by Matteo Maria Andreozzi 1 replies 141 views
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 12 days ago by Zax 2 replies 221 views