Release History

The latest Fast Models release version is reported at the top right of this page.

Details on What's New, and links to the Release Notes are provided below.

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Fast Models

Version 11.13

Released: December 09, 2020

What's new in 11.13

New features and enhancements

  • Support has been added for the following CPUs and System IP:
    • Cortex-A78C
    • Ethos-U55 NPU, currently for Linux hosts only.
    • Cortex-A78AE and Cortex-R82 Fast Models and FVPs are available as add-on packages on request.
  • The Corstone-300 FVP contains the Ethos-U55 model and is available free of charge at Arm Ecosystem FVPs.
  • The Cortex-M55 model supports Custom Datapath Extension (CDE).
  • System Register trace sources have been extended to capture CRm, CRn, opc0, opc1, and opc2 fields.
  • Visual Studio 2019 support has been added.
  • FastRAM is a new optimization feature which can bring significant speed improvements.

Deprecated and removed features

  • Model Shell and the related SimGen and System Canvas targets TARGET_MAXVIEW and TARGET_ISIM_DEPRECATED are deprecated.
  • AEMv8-A platforms are deprecated and will soon be replaced by AEMvA platforms.

Advance notice

Windows support will be added for the Ethos-U55 NPU model in a future release.

Release Note for Release History 11.13

Detailed documentation can be found in the Docs subfolder for Fast Models Portfolio and at https://developer.arm.com/products/system-design/fast-models/docs.

A significant number of the examples in Fast Models Portfolio 11.13 make use of images containing third party IP. These have been split out into a separate 'Third Party IP' package that can be downloaded from:

Not installing these images means that examples that require Dhrystone or the Linux images will not be functional, as well as examples using Accellera SystemC.

Enhancements and changes in Fast Models Portfolio 11.13

  • The Ethos-U55 NPU model has been added to the Fast Models Portfolio. It currently supports Linux hosts only. Windows support will follow in a subsequent release.

  • The Cortex-M55 model supports Custom Datapath Extension (CDE).

  • Cortex-A78AE and Cortex-R82 Fast Models are available as add-on packages on request. Contact support-esl@arm.com for more information.

  • System Register trace sources have been extended to capture CRm, CRn, opc0, opc1, and opc2 fields.

  • Visual Studio 2019 support has been added.

  • FastRAM optimization has been added.

    FastRAM is a cache of very large DMI pointers (64MB). When enabled, accesses to the platform RAM by the bus masters do not need to use the platform bus models at all, which can result in very significant speed improvements with complex platforms and workloads.

    See Fast Models User Guide for more information.

  • Cortex-A78C is included in the main package.

  • The combination of RHEL 6 and GCC6.4 is no longer supported.

Notice

  • To install the package without the need for user interaction, use the --i-accept-the-end-user-license-agreement command-line option.

    Note that using this option means you have read and accepted the terms and conditions of the End User License Agreement for the product and version installed.

  • Model Shell and the related SimGen and System Canvas targets (TARGET_MAXVIEW and TARGET_ISIM_DEPRECATED) are now deprecated. They will be removed in a future release.

  • Fast Models scheduler deprecation:

    This notice is intended for users who build simulation platforms running on the Fast Models scheduler and not the SystemC scheduler.

    Note that all the platforms and models delivered as part of the Fast Models package already use the SystemC scheduler, so this change only affects users who build their own platforms using Fast Models tools.

    Support for the Fast Models scheduler will be dropped in a future release. This means that support for dependent targets will be removed and any SimGen projects that depend on the Fast Models scheduler will fail to build.

    To find out if a project depends on the legacy scheduler, search for TARGET_ISIM_DEPRECATED = 1 or TARGET_MAXVIEW = 1 in an sgproj (SimGen project) file.

    You are advised to migrate from the Fast Models scheduler targets TARGET_ISIM_DEPRECATED = 1 and TARGET_MAXVIEW = 1 to the SystemC targets TARGET_SYSTEMC_ISIM = 1 and TARGET_SYSTEMC_MAXVIEW = 1 respectively. Either regenerate the sgproj files using sgcanvas or manually replace the entries in each .sgproj file affected as soon as possible.

  • CMN models .json file deprecation:

    Specifying a mesh topology by setting mesh_config_file to a .json file, as described in Fast Models Reference Manual is deprecated.

    From the next release, set mesh_config_file to the name of the yml configuration file generated by the Socrates tool.

  • AEMv8-A platforms are deprecated and will soon be replaced by AEMvA platforms which enable the current v8-A architecture and Future Architecture Technologies, selectable using parameters.

    For more information, contact support@arm.com

  • The trace fields for PVBusLogger have changed to include ExtendedID. Refer to the documentation.

  • FastRAM and trace enabling:

    • If you start the configuration file with 'T' and never use 'Q', then there will be trace for FastRAM for all the initialization and runtime.

    • If you end the file with 'T' and never use 'Q', then there will be trace for FastRAM for all runtime and not initialization.

    • If you start the file with 'T' and end the file with 'Q', then trace will be enabled only during FastRAM initialization.

    • Add one or more occurrences of 'T' and 'Q' in the file to trace parts of the initialization, according to where they occur in the file.

Fast Models limitations

This section contains limitations for models that are new in this release or new limitations that have been identified for existing models.

For more information, refer to the Fast Models Reference Manual at https://developer.arm.com/docs/100964/latest.

  • FastModels 11.13 adds a rel version of the GIC600-AE model supporting register accesses to the fault management unit and the RAS component, with the following functionality expectations:

    • FMU registers are enabled for read and write access with correct reset value.

    • Only secure-access is allowed for FMU registers.

    • Locking mechanism is based on FMU_KEY for FMU register write.

    • APB4 port from safety island to access FMU registers.

    • RAS registers are enabled for read and write access with correct reset value.

    • Parameters to set GICT_ERR<n>FR to individually enable error reporting are supported:

      • RAS-CFI-support: enable fault handling interrupt for corrected error.
      • RAS-UE-support: enable reporting for in-band uncorrected error.
      • RAS-FI-support: enable fault handling interrupt.
      • RAS-UI-support: enable error recovery interrupt for uncorrected error.
    • Access control for RAS registers is based on GICD_SAC. For the reset value, use parameter gict-allow-ns-reset.

    The GIC600-AE model has the following limitations:

    • Actual mechanism of FMU is not implemented yet such as ping/ack control.

    • Actual mechanism of RAS is not implemented yet such as getting notified by wrong ITS configuration or software error.

    • SPI collator is not supported.

    • po_reset signal with model is used for dbg_reset.

    • There is no domain reset.

    FastModels 11.13 adds support for the GIC600-AE registers GICR_CLASSR, GICD_ICLAR and read/write access to the register GICR_FCTLR, in addition to the reporting of the following RAS error types:

    • Software error record 0 for Redistributor on LPI: SYN_ITS_REG_SET_OOR, SYN_ITS_REG_CLR_OOR, SYN_ITS_REG_INV_OOR, SYN_ITS_REG_SET_ENB, SYN_ITS_REG_CLR_ENB, SYN_ITS_REG_INV_ENB.

    • Software error record 0 for Redistributor on configuration: SYN_ACE_BAD, SYN_PPI_PWRDWN, SYN_PPI_PWRCHANGE, SYN_GICR_ARE, SYN_PROPBASE, SYN_PENDBASE_ACC, SYN_LPI_CLR, SYN_WAKER_CHANGE, SYN_SLEEP_FAIL, SYN_PGE_ON_QUIESCE, SYN_PT_PROP_READ_FAIL.

    • Software error record 0 for Redistributor on table access: SYN_LPI_PROP_READ_FAIL, SYN_PT_TABLE_READ_FAIL, SYN_PT_TABLE_WRITE_FAIL.

      • Only Reading properties for individual LPIs, not block of LPIs, is modeled. Hence the reporting of the error types SYN_PT_PROP_READ_FAIL, SYN_PT_SUB_TABLE_READ_FAIL and SYN_PT_TABLE_WRITE_FAIL_BYTE is not modeled.

      • The reporting of the error types SYN_PT_COARSE_MAP_READ_FAIL and SYN_PT_COARSE_MAP_WRITE_FAIL is not modeled.

    • Software error record 0 for Distributor: SYN_ACE_BAD, SYN_GICR_ARE, SYN_GICD_CTLR, SYN_SGI_NO_TGT, SYN_SPI_BLOCK, SYN_SPI_OOR, SYN_SPI_NO_DEST_TGT, SYN_DEACT_IN, SYN_SPI_CHIP_OFFLINE, SYN_SPI_NO_DEST_IOFN.

      The reporting of the error type SYN_GICD_CORRUPTED is not modeled.

    • Software error record 0 for ITS: SYN_ACE_BAD.

      The reporting of the error type SYN_ITS_OFF is not modeled.

    • Software error record 13 for MAP* commands: MAPD_DEVICE_OOR, MAPD_ITTSIZE_OOR, MAPC_COLLECTION_OOR, MAPC_TGT_OOR, MAPC_LPI_OFF, MAPI_DEVICE_OOR, MAPI_COLLECTION_OOR, MAPI_ID_OO, MAPI_UNMAPPED_DEVICE, MAPVI_DEVICE_OOR, MAPVI_COLLECTION_OOR, MAPVI_UNMAPPED_DEVICE, MAPVI_ID_OOR, MAPVI_PHYSICALID_OOR.

      The reporting of the error type MAPC_CHIP_OFFLINE_OOR is not modeled.

  • DynamIQ (FCM):

    For flexible Cortex-A55+Cortex-A75 clusters, there is a known issue related to presentation of parameters and CADI targetNames to CADI clients when cpu instances in the first subcluster are configured to be less than 4. CADI targetNames and parameters for cpu[0-3] are always shown from the Cortex-A55 subcluster, when viewed by CADI clients.

  • DMC-620 Dynamic Memory Controller Fast Model:

    • No support for address striping.
    • Works with linear addresses and not in rank,bank,row,column form.
    • Includes error injection and detection mechanisms and syndrome registers support only for 2 out of the 6 RAS error types.
    • Scrubbing functionality is not provided.
    • Does not implement direct read or write commands.
    • Does not implement any performance counters.
  • CMN-600 Coherent Mesh Network:

    • The model implements version r1p1 of the RTL specification and includes CAL (Component Aggregation Layer) functionality that was added in r3p0.
    • The model supports a new revision parameter to select between r1p1 and r3p0 implementations.
    • CAL r2 and r3 features are supported. Further testing of these features is planned.
    • The following CML (Coherent Multi-chip Links) r3 features are supported:
      • LDID-based CML routing
      • CCIX port aggregation support
      Further testing of these features is planned.
  • Pipeline Model plug-in:

    For the InOrder PipelineModel source example plugin, libtinfo-dev needs to be installed on Ubuntu 16.04.

  • The cp15sdisable port/parameter is removed from some cores that do not support AArch32 at EL3.

Compilers and Operating Systems supported by Fast Models

  • RedHat 6 with GCC 4.9.2.
  • RedHat 7 with GCC 6.4.0 and GCC 4.9.2.
  • Ubuntu 16.04 with GCC 6.4.0 and GCC 7.3.0.
  • Ubuntu 18.04 with GCC 7.3.0.
  • Windows 10 with Visual Studio 2017 version 15.9.11 or later.
  • Windows 10 with Visual Studio 2019 version 16.7.3 or later.
  • The following Visual Studio components are required:
    • Visual C++ ATL for x86 and x64.
    • Visual C++ MFC for x86 and x64.
  • Windows SDK version 10.0.16299.0 or later is required for Visual Studio 2019 support.

Hardware requirements for Generic Graphics Accelerator (GGA)

GGA has been validated on the NVIDIA GT 730 or later graphics cards with the following driver versions:

  • 390.77 and above for Ubuntu.
  • 390.77 and above for Windows.

FLEXnet license management utilities

FLEXnet server binaries are no longer shipped with the product; if you need them, download them from https://developer.arm.com/products/software-development-tools/license-management/downloads.

If you are using floating licenses, Fast Models 11.12 requires FLEXnet server version 11.16.6.0 or later. Please plan to upgrade your license server accordingly.

Linaro images and command lines tested in this release

All A-profile platforms available in this release have been validated against the following Linaro images: Android 18.07 for v8-A platforms and Android 15.03 for v7-A platforms.

The command lines tested are:

  • v8-A (examples):

    FVP_Base_AEMv8A-AEMv8A \
    -C pctl.startup=0.0.0.0 -C bp.secure_memory=0 -C cache_state_modelled=0 -C bp.pl011_uart0.untimed_fifos=1 \
    -C bp.secureflashloader.fname=bl1.bin -C bp.flashloader0.fname=fip.bin \
    -C bp.ve_sysregs.mmbSiteDefault=0 -C bp.virtioblockdevice.image_path=fvp.img \
    --data cluster0.cpu0=Image@0x80080000 \
    --data cluster0.cpu0=fdt.dtb@0x82000000 \
    --data cluster0.cpu0=ramdisk.img@0x84000000
    EVS_Base_AEMv8A-AEMv8A.x \
    -C Base.pctl.startup=0.0.0.0 -C Base.bp.secure_memory=0 -C Base.cache_state_modelled=0 -C Base.bp.pl011_uart0.untimed_fifos=1 \
    -C Base.bp.secureflashloader.fname=bl1.bin -C Base.bp.flashloader0.fname=fip.bin \
    -C Base.bp.ve_sysregs.mmbSiteDefault=0 -C Base.bp.virtioblockdevice.image_path=fvp.img \
    --data Image@0x80080000 \
    --data fdt.dtb@0x82000000 \
    --data ramdisk.img@0x84000000
    (This command line is also valid for SVPs)
  • v7-A (examples):

    FVP_VE_Cortex-A15x1-A7x1 \
    -C motherboard.flashloader0.fname=boot/rtsm/uefi_rtsm_ve-ca15.bin -C motherboard.flashloader1.fname=uefi-vars.fd \
    -C motherboard.flashloader1.fnameWrite=uefi-vars.fd -C motherboard.mmc.p_mmc_file=linaro.img \
    -C motherboard.pl011_uart0.unbuffered_output=true -C motherboard.smsc_91c111.enabled=1 \
    -C motherboard.hostbridge.userNetworking=1
    EVS_LinuxBoot_Cortex-A15x2 \
    -C Base.motherboard.flashloader0.fname=boot/rtsm/uefi_rtsm_ve-ca15.bin -C Base.motherboard.flashloader1.fname=uefi-vars.fd \
    -C Base.motherboard.flashloader1.fnameWrite=uefi-vars.fd -C Base.motherboard.mmc.p_mmc_file=linaro.img \
    -C Base.motherboard.pl011_uart0.unbuffered_output=true -C Base.motherboard.smsc_91c111.enabled=1 \
    -C Base.motherboard.hostbridge.userNetworking=1
    (This command line is also valid for SVPs)

Outstanding issues

  • GGA issues:

    • On Windows hosts, a Linux target OS running Wayland has known issues.

  • There is no log output from an FVP using the --iris-log option. There is a workaround by setting the environment variable IRIS_GLOBAL_INSTANCE_LOG_MESSAGES =1 to enable logging.

  • Setting R52 flash and llpp size to zero is not sufficient to make them unrouteable.

  • Models only support some types of memory breakpoints. Currently the error message returned if an unsupported type is used might not clearly indicate that the breakpoint type is unsupported.

  • CADI methods deprecated for use in Fast Models 11.13:

    • CADICallbackObj
      • appliOpen()
      • appliClose()
      • cycleTick()
      • killInterface()
  • A15 bus transactions are not bus accurate.

  • CADI and MTI names for CP15 registers are different.

  • When semihosting is enabled on a SystemC model and a read from stdin is done within the target software, the semihosting call from CADI does not originate from the SystemC thread. Consequently the complete simulation becomes blocked if the semihosting call cannot complete due to no user input.

  • In some circumstances, the model will boot more slowly when an operating system filesystem image is used in read-only mode. The workaround is to make sure that the image is writeable.

  • Cortex-A53, Cortex-A35 and Cortex-A32 lack the Advanced SIMD Engine-present parameter.

  • A17 BROADCAST parameters should be at the cluster level, not at the cpu level.

  • DynamIQ does not support all cluster models.

  • On Linux, a program that dynamically loads a model shared object file using dlopen() must be linked with the pthread library (-lpthread), even if the program is otherwise single-threaded. Failure to do so may result in a segmentation fault, or other abnormal termination, possibly with the message 'Enable multithreading to use std::thread: Operation not permitted', depending on the libstdc++ version. The underlying defect is a libstdc++ bug (#67791) which has been exposed by migrating the model to C++11 threads.

  • CCN5xx models do not expose CCNCache sub-component parameters in System Canvas.

Outstanding tools issues

  • Model Debugger does not display the correct values for wTasKMaskId.

  • The Cortex-M0 model exposes a VTOR register via CADI, but this register in not present in hardware.

  • On Windows, .bmp files are copied into the top Build folder for FVP_MPS2 models. They are not accessible to the isim_system generated in the internal platform/flavor dependent folder. An easy workaround is to manually copy them into that folder.

  • Neoverse-N1/Neoverse-E1 Fast Models:

    • DBGEN, SPIDEN, NIDEN, and SPIDEN signals in the model have per-core instances instead of per-cluster.
    • The cfgsdisable signal will be removed in a future release.

Feedback on this product

If you have any comments or suggestions about this product, contact support-esl@arm.com and give:

  • The product name.

  • The product revision or version.

  • An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate.