Release History

The latest Fast Models release version is reported at the top right of this page.

Details on What's New, and links to the Release Notes are provided below.

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Fast Models

Version 11.4

Released: June 21, 2018

What's new in 11.4

New features and enhancements

  • New CTModels for Cortex-A76, with several new example FVP_Base platforms.
  • New CTModel for Cortex-M35P and new Build_Cortex-M35P example FVP_MPS2 platform.
  • Added support for compiler GCC-6.4.0.

Deprecated and removed features

  • GGA (Generic Graphics Accelerator) and GRM (Graphics Register Model) are not supported in this release.
  • The zstdint.h and zinttypes.h headers are deprecated. Use the standard cstdint and cinttypes files instead.

Release Note for Release History 11.4

Detailed documentation can be found in the 'Docs' subfolder for Fast Models Portfolio.

A significant number of the examples in Fast Models Portfolio 11.4 make use of images containing third party IP. These have been split out into a separate 'Third Party IP' package that can be downloaded from:

Not installing these images will mean that examples that require Dhrystone or the Linux images will not be functional, as well as examples using Accellera SystemC 2.3.1.

Enhancements and Changes in Fast Models Portfolio 11.4

  • Added support for Cortex-A76 CTModel with the following new FVPs:

    • Build_Cortex-A76
    • Build_Cortex-A76x1
    • Build_Cortex-A76x2
    • Build_Cortex-A76x4
    • Build_Cortex-A55+Cortex-A76
    • Build_Cortex-A55x4+Cortex-A76x2
  • Added support for compiler GCC-6.4.0.

  • GGA (Generic Graphics Accelerator) and GRM (Graphics Register Model) are not supported for Mali graphics processors in this release.

  • Added support for Cortex-M35P CTModel with the file ARMCortexM35PCT.lisa. This package supports the Build_Cortex-M35P example FVP_MPS2 platform.


    • The model does not implement any physical security features.
    • Bits[3:0] of the Anti-tampering Features Control Register are supported for read/write. No functionality is implemented.
    • Read/write access to the Anti-tampering Features Control Register is supported using SECKEY. No functionality is implemented.
    • Cache is not supported in the Cortex-M35P Fast Model.


  • The folder structure in FastModelsPortfolio will be refactored in a future release.

  • The default parameter values for HostBridge and VirtioNet will change in a future release.

  • Model Shell and the related SimGen target (TARGET_MAXVIEW) are now deprecated. They will be removed from Fast Models in a future release.

  • Support for compiler Visual Studio 2013 will be removed in the Nov '18 release.

  • Support for compilers GCC-4.8.3 and GCC-4.8.4 will be removed in the Nov '18 release.

  • The zstdint.h and zinttypes.h supplied headers are deprecated and will be removed from the product in the future. Use the standard cstdint and cinttypes files instead.

  • The example platform FVP_Base_AEMv8A-AEMv8A-DP550-V61 will be removed in the next release.

Fast Models limitations

  • Cortex-A76:

    • BROADCASTCACHEMAINTPOU pin is not implemented.
    • COREINSTRRET,COREINSTRRUN,nPMBIRQ signals are not implemented.
    • 256-bit wide output transactions are not supported.
    • Error correction/detection features are not supported.
    • Self-test features (MBIST) are not supported.
    • Latency configuration is not supported.
    • Snoop filtering is not supported.
    • Cache stashing capability is not supported.
  • CMN-600:

    • PMU counters are not supported (counter registers are implemented as RAZ).
    • All RNI and RND nodes control 3 interface ports. The other variants which control 2 or 1 ports are not supported.
    • QoS is not supported and all related registers are RAZ/WI.
    • Error injection and Error generation is not supported. All error registers are RAZ/WI.
    • Power/Clock/Interrupt signals are not supported.
    • HN-T nodes are not supported.
    • CAL (Core Aggregation Layer) always support up to 4 devices.
    • Atomic operations to noncachable/device regions are not supported.
    • By default, HNF hashing uses the address[12:MAX] instead of the actual address[6:MAX], due to the DMI mechanism in the model. Enable the parameter enable_snf_hashing to make hashing logic use the actual address[6:MAX].
    • There are no constraints on mesh sizing when XID_WIDTH and YID_WIDTH = 4.
    • RM-SAM GIC memory region is not supported.
    • The CML feature is not supported.

Compilers and Operating Systems supported by Fast Models

  • RedHat 6
  • RedHat 7
  • Ubuntu 14.04
  • Ubuntu 16.04
  • Windows 7
  • Windows 10
  • GCC-4.8.3 and GCC-4.8.4
  • GCC-4.9.2
  • GCC-5.4.0
  • GCC-6.4.0
  • Visual Studio 2013 - Update 4
  • Visual Studio 2015 - Update 3
  • The following warning is produced when compiling Fast Models with Visual Studio 2015: Unknown compiler version - please run the configure tests and report the results. This occurs due to the Accellera SystemC library using an older version of the Boost library which is not aware of any versions after Visual Studio 2013.

FLEXnet license management utilities

FLEXnet server binaries are no longer shipped with the product; if you need them, download them from

Release 11.4 of Fast Models requires a newer version of the FLEXnet license management utilities. If you are using floating licenses, you need to upgrade to version (or later) of the FLEXnet license management utilities. Prior versions are not compatible.

License queueing support

When using floating licenses, if all available licenses are in use, models and tools can be configured to queue until a license is available. This is enabled by setting the environment variable FM_LICENSE_QUEUE_TIMEOUT to a timeout value in seconds. The default value of 0 disables this feature.

Note that enabling this feature may cause model initialisation to take a long time, as models will wait for a license to become available until the timeout period expires, rather than failing immediately.

Linaro images and command lines tested in this release

All A-profile platforms available in this release have been validated against the following Linaro images: Android 16.12 for v8-A platforms and Android 15.03 for v7-A platforms.

The command lines tested are:

  • v8-A:

    FVP_Base_AEMv8A-AEMv8A \
    -C pctl.startup= -C bp.secure_memory=0 -C cache_state_modelled=0 -C bp.pl011_uart0.untimed_fifos=1 \
    -C bp.secureflashloader.fname=bl1.bin -C bp.flashloader0.fname=fip.bin \
    -C bp.ve_sysregs.mmbSiteDefault=0 -C bp.virtioblockdevice.image_path=fvp.img \
    --data cluster0.cpu0=Image@0x80080000 \
    --data cluster0.cpu0=fdt.dtb@0x82000000 \
    --data cluster0.cpu0=ramdisk.img@0x84000000
    EVS_Base_AEMv8A-AEMv8A.x \
    -C Base.pctl.startup= -C Base.bp.secure_memory=0 -C Base.cache_state_modelled=0 -C Base.bp.pl011_uart0.untimed_fifos=1 \
    -C Base.bp.secureflashloader.fname=bl1.bin -C Base.bp.flashloader0.fname=fip.bin \
    -C Base.bp.ve_sysregs.mmbSiteDefault=0 -C Base.bp.virtioblockdevice.image_path=fvp.img \
    --data Image@0x80080000 \
    --data fdt.dtb@0x82000000 \
    --data ramdisk.img@0x84000000
    (This command line is also valid for SVPs)
  • v7-A:

    FVP_VE_Cortex-A15x1-A7x1 \
    -C motherboard.flashloader0.fname=boot/rtsm/uefi_rtsm_ve-ca15.bin -C motherboard.flashloader1.fname=uefi-vars.fd \
    -C motherboard.flashloader1.fnameWrite=uefi-vars.fd -C motherboard.mmc.p_mmc_file=linaro.img \
    -C motherboard.pl011_uart0.unbuffered_output=true -C motherboard.smsc_91c111.enabled=1 \
    -C motherboard.hostbridge.userNetworking=1
    EVS_LinuxBoot_Cortex-A15x2 \
    -C Base.motherboard.flashloader0.fname=boot/rtsm/uefi_rtsm_ve-ca15.bin -C Base.motherboard.flashloader1.fname=uefi-vars.fd \
    -C Base.motherboard.flashloader1.fnameWrite=uefi-vars.fd -C Base.motherboard.mmc.p_mmc_file=linaro.img \
    -C Base.motherboard.pl011_uart0.unbuffered_output=true -C Base.motherboard.smsc_91c111.enabled=1 \
    -C Base.motherboard.hostbridge.userNetworking=1
    (This command line is also valid for SVPs)

Outstanding CTModel issues

  • Models only support some types of memory breakpoints. Currently the error message returned if an unsupported type is used may not clearly indicate that the breakpoint type is unsupported.

  • CADI methods deprecated for use in Fast Models 11.4:

    • CADICallbackObj
      • appliOpen()
      • appliClose()
      • cycleTick()
      • killInterface()
  • When attempting to debug an ISIM system, if you launch Model Debugger from System Canvas and then specify an application to load this causes an error in Model Debugger (Error using application...), and the model and application fail to load.

    Workaround: Launch Model Debugger without specifying an application, and then load the application from within Model Debugger itself using File -> Load Application Code.

  • A15 bus transactions are not bus accurate.

  • CADI and MTI names for CP15 registers are different.

  • Cache state modelling configuration is now verified at simulation start and the simulation will exit with an error message if an incorrect configuration is detected in the platform. For example:

    Error: MyPlatform: Incompatible Cache Configuration
    Cache state modelling is on in my_platform.cci
    Cache state modelling is off in my_platform.core.l2_cache
  • PVBus Fan out is not supported and a bus decoder is required in order to do this.

  • When semi-hosting is enabled on SystemC model and a read from stdin is done within the target software, the semi-hosting call from CADI does not originate from the SystemC thread. Consequently the complete simulation becomes blocked if the semi-hosting call cannot complete due to no user input.

  • Cache models may output debug messages on stderr even with --quiet.

  • The Watchpoint mask does not have the expected effect.

  • When writing to MDSCR_EL1.SS on AEMv8A, it does not change status until an ERET is executed. This should be consistently managed by the has_delayed_sysreg parameter.

  • In some circumstances, the model will boot more slowly when an operating system filesystem image is used in read-only mode. The workaround is to make sure that the image is writeable.

  • The shareable override functionality of CCI400 does not work. The slave interface shareable override register exists and may be read and written but has no functionality.

  • The value of cpu.register_reset_data and cpu.scramble_unknowns_at_reset should be reflected in the bits of CNTHCTL_EL2 which reset value is UNKNOWN.

  • When EL3 == AArch32 and executing in AArch32 Secure EL1 (SVC_s), an update of the CNTP_CTL_S causes the tarmac log to print an update of CNTPS_CTL_EL1.

  • Breakpoints must be set after loading the image to be run, otherwise these will not be hit during execution even if the addresses are accessed.

  • Cortex-A53, A35 and A32 lack the Advanced SIMD Engine-present parameter.

  • A17 BROADCAST parameters should be at cluster level, not cpu level.

  • CADIExecReset is no longer supported and CADIExecGetResetLevels does not throw an error.

  • DynamIQ does not support all cluster models.

Outstanding tools issues

  • ModelDebugger does not display the correct values for wTasKMaskId.

  • The Cortex-M0 model exposes a VTOR register via CADI, but this register in not present in hardware.

  • On Windows, .bmp files are copied into the top Build folder for FVP_MPS2 models. They are not accessible to the isim_system generated in the internal platform/flavor dependent folder. An easy workaround is to manually copy them into that folder.

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