What's new in 11.7
New features and enhancements
- Updated End User License Agreement (EULA).
- Support for Cortex-A65 and Cortex-A77 Fast Models and platforms.
- Support for Cortex-M33 and AEMv8M coprocessor.
- Support for Component Aggregation Layer (CAL) in the CMN-600 model.
- Full support for VC2017.
- Armv8.5-A support at Release quality.
Release Note for Release History 11.7
Detailed documentation can be found in the Docs subfolder for Fast Models Portfolio and at https://developer.arm.com/products/system-design/fast-models/docs.
A significant number of the examples in Fast Models Portfolio 11.7 make use of images containing third party IP. These have been split out into a separate 'Third Party IP' package that can be downloaded from:
Not installing these images means that examples that require Dhrystone or the Linux images will not be functional, as well as examples using Accellera SystemC 2.3.2.
Enhancements and changes in Fast Models Portfolio 11.7
As part of our licensing simplification project, Fast Models 11.7 updates the End User License Agreement (EULA). The new EULA aligns with other Arm software products, giving a consistent set of terms and conditions across products.
Support for Cortex-A65 and Cortex-A77 Fast Models and platforms.
Support for Cortex-M33 and AEMv8M co-processor.
Support for Component Aggregation Layer (CAL) has been added to the CMN-600 model.
Full support for VC2017 has been added in this release. For a full list of supported platforms, see the list below entitled "Compilers and Operating Systems supported by Fast Models".
Armv8.5-A support is available at Release quality.
Cortex-R52 - the HRMR.RR bit now raises signal WARMRSTREQx. In other words, a request is generated to reset the controller to handle the warm reset. If this pin is not connected in a platform then the core does the self reset.
We plan to deprecate GCC 4.9.2 in the 11.8 release.
We plan to deprecate Ubuntu 14.04 in the 11.8 release.
We plan to update zlib to 1.2.11 and ffmpeg to 4.1.3. This will only affect users of the Mali video processor models.
The folder structure in Fast Models Portfolio will be refactored in a future release.
The default parameter values for HostBridge and VirtioNet will change in a future release.
Model Shell and the related SimGen target (TARGET_MAXVIEW) are deprecated. They will be removed from Fast Models in a future release.
The zstdint.h and zinttypes.h supplied headers are deprecated and will be removed from the product in the future. Use the standard cstdint and cinttypes files instead.
The TxThread.h and TxRunnable.h supplied headers, and the TxThread and TxRunnable types, are deprecated and will be removed from the product in the future. Use the standard library thread facilities instead.
Support for MxScript will be removed from Model Debugger in a future release. Use Iris Python Debug Scripting instead.
Fast Models limitations
This section contains information on model limitations for models that are new in this release or new limitations that have been identified for previously released models.
For more information, refer to the Fast Models Reference Manual at: https://developer.arm.com/docs/100964/latest.
Improvements to ClockTimer component to ensure clocks run correctly when switching frequencies:
Previously, it was possible for a Clock component to run even if the connection to the clk_in input was missing. This is no longer possible and designs that erroneously relied on the old behavior might not function correctly. For example, software running on the design might hang.
For flexible Cortex-A55+Cortex-A75 clusters, there is a known issue related to presentation of parameters and CADI targetNames to CADI clients when cpu instances in the first subcluster are configured to be less than 4. CADI targetNames and parameters for cpu[0-3] are always shown from the Cortex-A55 subcluster, when viewed by CADI clients.
DMC-620 Dynamic Memory Controller Fast Model:
- No support for address striping.
- Works with linear addresses and not in rank,bank,row,column form.
- Includes error injection and detection mechanisms and syndrome registers support only for 2 out of the 6 RAS error types.
- Scrubbing functionality is not provided.
- Does not implement direct read or write commands.
- Does not implement any performance counters.
CMN-600 Coherent Mesh Network:
- The model implements version r1p1 of the RTL specification and includes CAL (Component Aggregation Layer) functionality that was added in r3p0.
- The model supports a new revision parameter to select between r1p1 and r3p0 implementations.
- CAL r2 and r3 features are supported. Further testing of these features is planned.
Pipeline Model plug-in:
For the InOrder PipelineModel source example plugin, "libtinfo-dev" needs to be installed on Ubuntu 16.04.
cp15sdisable port/parameter is removed from some cores that do not support AArch32 at EL3.
Compilers and Operating Systems supported by Fast Models
- RedHat 6
- RedHat 7
- Ubuntu 14.04
- Ubuntu 16.04
- Windows 7
- Windows 10
- Visual Studio 2015 - Update 3
- Visual Studio 2017. The following Visual Studio 2017 components are required:
- Visual C++ ATL for x86 and x64.
- Visual C++ MFC for x86 and x64.
Hardware Requirements for Generic Graphics Accelerator / GGA
GGA has been validated on the NVIDIA GT 730 or later graphics cards with the following driver versions:
- 390.77 and above for Ubuntu.
- 390.77 and above for Windows.
FLEXnet license management utilities
FLEXnet server binaries are no longer shipped with the product; if you need them, download them from https://developer.arm.com/products/software-development-tools/license-management/downloads.
Release 11.7 of Fast Models requires a newer version of the FLEXnet license management utilities. If you are using floating licenses, you need to upgrade to version 188.8.131.52 (or later) of the FLEXnet license management utilities. Prior versions are not compatible.
Linaro images and command lines tested in this release
All A-profile platforms available in this release have been validated against the following Linaro images: Android 18.07 for v8-A platforms and Android 15.03 for v7-A platforms.
The command lines tested are:
FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 -C bp.secure_memory=0 -C cache_state_modelled=0 -C bp.pl011_uart0.untimed_fifos=1 \ -C bp.secureflashloader.fname=bl1.bin -C bp.flashloader0.fname=fip.bin \ -C bp.ve_sysregs.mmbSiteDefault=0 -C bp.virtioblockdevice.image_path=fvp.img \ --data cluster0.cpu0=Image@0x80080000 \ --data cluster0.cpu0=fdt.dtb@0x82000000 \ --data cluster0.cpu0=ramdisk.img@0x84000000
EVS_Base_AEMv8A-AEMv8A.x \ -C Base.pctl.startup=0.0.0.0 -C Base.bp.secure_memory=0 -C Base.cache_state_modelled=0 -C Base.bp.pl011_uart0.untimed_fifos=1 \ -C Base.bp.secureflashloader.fname=bl1.bin -C Base.bp.flashloader0.fname=fip.bin \ -C Base.bp.ve_sysregs.mmbSiteDefault=0 -C Base.bp.virtioblockdevice.image_path=fvp.img \ --data Image@0x80080000 \ --data fdt.dtb@0x82000000 \ --data ramdisk.img@0x84000000(This command line is also valid for SVPs)
FVP_VE_Cortex-A15x1-A7x1 \ -C motherboard.flashloader0.fname=boot/rtsm/uefi_rtsm_ve-ca15.bin -C motherboard.flashloader1.fname=uefi-vars.fd \ -C motherboard.flashloader1.fnameWrite=uefi-vars.fd -C motherboard.mmc.p_mmc_file=linaro.img \ -C motherboard.pl011_uart0.unbuffered_output=true -C motherboard.smsc_91c111.enabled=1 \ -C motherboard.hostbridge.userNetworking=1
EVS_LinuxBoot_Cortex-A15x2 \ -C Base.motherboard.flashloader0.fname=boot/rtsm/uefi_rtsm_ve-ca15.bin -C Base.motherboard.flashloader1.fname=uefi-vars.fd \ -C Base.motherboard.flashloader1.fnameWrite=uefi-vars.fd -C Base.motherboard.mmc.p_mmc_file=linaro.img \ -C Base.motherboard.pl011_uart0.unbuffered_output=true -C Base.motherboard.smsc_91c111.enabled=1 \ -C Base.motherboard.hostbridge.userNetworking=1(This command line is also valid for SVPs)
- Semihosting hangs with Iris clients. Running a workload on a core model that attempts to read semihosted input, with an external Iris client attached to the model, might cause the model to hang indefinitely.
- PMU registers mismatch. SPE register space is not fully compliant yet.
- There is a performance issue with in-process trace using Iris compared to trace using MTI.
Models only support some types of memory breakpoints. Currently the error message returned if an unsupported type is used might not clearly indicate that the breakpoint type is unsupported.
CADI methods deprecated for use in Fast Models 11.7:
When attempting to debug an ISIM system, if you launch Model Debugger from System Canvas and then specify an application to load, this causes an error in Model Debugger (Error using application...), and the model and application fail to load.
Workaround: Launch Model Debugger without specifying an application, and then load the application from within Model Debugger itself using File -> Load Application Code.
A15 bus transactions are not bus accurate.
CADI and MTI names for CP15 registers are different.
When semihosting is enabled on a SystemC model and a read from stdin is done within the target software, the semihosting call from CADI does not originate from the SystemC thread. Consequently the complete simulation becomes blocked if the semihosting call cannot complete due to no user input.
Cache models may output debug messages on stderr even with --quiet.
The Watchpoint mask does not have the expected effect.
When writing to MDSCR_EL1.SS on AEMv8A, it does not change status until an ERET is executed. This should be consistently managed by the has_delayed_sysreg parameter.
In some circumstances, the model will boot more slowly when an operating system filesystem image is used in read-only mode. The workaround is to make sure that the image is writeable.
The shareable override functionality of CCI400 does not work. The slave interface shareable override register exists and may be read and written but has no functionality.
The value of cpu.register_reset_data and cpu.scramble_unknowns_at_reset should be reflected in the bits of CNTHCTL_EL2 which reset value is UNKNOWN.
When EL3 == AArch32 and executing in AArch32 Secure EL1 (SVC_s), an update of the CNTP_CTL_S causes the tarmac log to print an update of CNTPS_CTL_EL1.
Breakpoints must be set after loading the image to be run, otherwise these will not be hit during execution even if the addresses are accessed.
Cortex-A53, A35, and A32 lack the Advanced SIMD Engine-present parameter.
A17 BROADCAST parameters should be at cluster level, not cpu level.
DynamIQ does not support all cluster models.
On Linux, a program that dynamically loads a model shared object file using dlopen() must be linked with the pthread library (-lpthread), even if the program is otherwise single-threaded. Failure to do so may result in a segmentation fault, or other abnormal termination, possibly with the message 'Enable multithreading to use std::thread: Operation not permitted', depending on the libstdc++ version. The underlying defect is a libstdc++ bug (#67791) which has been exposed by migrating the model to C++11 threads.
Outstanding tools issues
Model Debugger does not display the correct values for wTasKMaskId.
The Cortex-M0 model exposes a VTOR register via CADI, but this register in not present in hardware.
On Windows, .bmp files are copied into the top Build folder for FVP_MPS2 models. They are not accessible to the isim_system generated in the internal platform/flavor dependent folder. An easy workaround is to manually copy them into that folder.
Neoverse-N1/Neoverse-E1 Fast Models:
- DBGEN, SPIDEN, NIDEN, and SPIDEN signals in the model have per-core instances instead of per-cluster.
- The cfgsdisable signal will be removed in a future release.
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