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Specifications

Cortex-A320 is the smallest implementation of the Armv9 architecture, bringing the latest innovations in security and ML processing to the efficient tier of Cortex-A processors. Cortex-A320 provides significant ML performance improvements of up to 10x compared to Cortex-A35 and a notable uplift in scalar performance of up to 33% over Cortex-A35. This also integrates the latest Armv9 security features, including MTE, PAC/BTI and Secure EL2, all of which help to improve security for the next generation of edge AI devices.

Cortex-A320 block diagram
Architecture Armv9.2-A (Harvard)
Extensions
  • Up to Armv8.7 extensions
  • QARMA3 extensions
  • SVE2 extensions
  • Memory Tagging Extensions (MTE) (including Asymmetric MTE)
  • Cryptography extensions
  • RAS extensions
Microarchitecture Pipeline In order
Superscalar Partial
Neon/Floating Point Unit Yes
Cryptography Unit Optional
Max number of CPUs in cluster 4
Physical Addressing (PA) 40-bit
Core architecture Armv9.2-A
Memory system and external interfaces L1 I-Cache / D-Cache 32KB or 64KB
L2 Cache Optional, 128KB, 192KB, 256KB, 384KB, 512KB
L3 Cache No
ECC Support Yes
Bus interfaces AMBA AXI5
ACP No
Peripheral Port No
Other Security TrustZone, Secure EL2, MTE, PAC/BTI
Interrupts GIC interface, GICv4.1
Generic timer Armv9.2-A
PMU PMUv3.7
Debug Armv9.2-A
CoreSight CoreSightv3
Embedded Trace Extension ETEv1.1
Trace Buffer Extension Yes

Tools and Software

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Works Well With

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Debug and trace software that runs on Arm-based system-on-chips.

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Memory controllers to optimize efficient access to DRAM.