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The CMSIS is a vendor-independent hardware abstraction layer for microcontrollers that are based on Arm® Cortex® processors. It defines generic tool interfaces and enables consistent device support. Its software interfaces simplify software re-use, reduce the learning curve for microcontroller developers, and improve time to market for new devices.

The CMSIS provides interfaces to processor and peripherals, real-time operating systems, and middleware components. It includes a delivery mechanism for devices, boards, and software and enables the combination of software components from multiple vendors.

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CMSIS Components

CMSIS-... Target Processors
Description
Core(M) All Cortex-M, SecurCore
Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.
Core(A) Cortex-A5/A7/A9 Standardized API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.
Driver All Cortex Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.
DSP All Cortex-M DSP library collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P.
NN All Cortex-M Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.
RTOS v1
 Cortex-M0/M0+/M3/M4/M7 Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.
RTOS v2
 All Cortex-M, Cortex-A5/A7/A9  Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface.
Pack All Cortex-M, SecurCore, Cortex-A5/A7/A9 Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM).
SVD All Cortex-M, SecurCore Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.
DAP All Cortex Firmware for a debug unit that interfaces to the CoreSight Debug Access Port.
Zone All Cortex-M Defines methods to describe system resources and to partition these resources into multiple projects and execution areas.