Platform Security Architecture

The Platform Security Architecture (PSA) is a holistic set of threat models, security analyses, hardware and firmware architecture specifications, and an open source firmware reference implementation. PSA provides a recipe, based on industry best practice, that allows security to be consistently designed in, at both a hardware and firmware level.

PSA is a contribution from Arm to the entire IoT ecosystem, from chip designers and device developers to cloud and network infrastructure providers and software vendors.

PSA is scalable for all connected devices, offering common ground rules and a more economical approach to building more secure devices.

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Four key phases of PSA 

Analyze

The analyze phase offers a set of freely available example threat models and security analyses (TMSA) for three common IoT use cases. The goal of this stage is to analyze the threats that have the potential to compromise your device and generate a set of security requirements, based on the risks.

Architect

The architect phase contains a set of freely available hardware and firmware specifications that allow you to design-in the necessary security requirements for your device. These specifications include the PSA Security Model (PSA-SM), Trusted Base System Architecture for M-Profile (TBSA-M), PSA Firmware Framework (PSA-FF), Trusted Boot Firmware Update (TBFU). The PSA Security Model provides important terminology and methodology for PSA and informs the use of the other PSA specifications.

Implement

The implement phase provides an open source firmware reference implementation, APIs and an API test suite. Trusted Firmware-M is a reference implementation of secure world software. It provides SoC developers and OEMs with a reference trusted code base that complies with the PSA specifications.

Additionally, there are three sets of PSA APIs: PSA Developer APIs for RTOS and software developers, PSA Firmware Framework APIs for security specialists, and TBSA APIs for silicon manufacturers.

Certify

The certify phase, known as PSA Certified™, is an independent testing scheme developed by Arm and its security partners. The scheme is split into two key areas: PSA Functional API Certification and PSA Certified.

PSA Functional API Certification checks that software uses PSA interfaces correctly, through an API test suite.

PSA Certified consists of three progressive levels of assurance and robustness, enabling device makers to choose solutions appropriate to their use case.


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PSA security framework

  • PSA Functional API Certification checks compliance to PSA architectural specifications.
  • PSA Certified tests that the correct level of security robustness has been implemented, as defined by the analyze phase.

Platform Security Architecture security evaluation block diagram.


Platform Security Architecture Information Block Diagram.

Standardized isolation

  • Designed to secure low cost IoT devices, where a full Trusted Execution Environment (TEE) would not be appropriate
  • PSA protects sensitive assets (keys, credentials and firmware) by separating these from the application firmware and hardware
  • PSA defines a Secure Processing Environment (SPE) for this data, the code that manages it and its trusted hardware resources
  • PSA is architecture agnostic and can be implemented on Cortex-M, Cortex-R and Cortex-A-based devices
  • The initial focus is Cortex-M-based devices


Platform Security Architecture Standardized Interfaces Diagram.

Standardized interfaces

  • PSA specifies interfaces to decouple components:
    • Enables reuse of components in other device platforms
    • Reduces integration effort
  • Partners can provide alternative implementations:
    • Necessary to address different cost, footprint, regulatory or security needs
  • PSA provides an architectural specification:
    • Hardware, firmware and process requirements and interfaces

Example of IoT device implementation diagram

Example of IoT device implementation

  • OEMs can choose their preferred implementations.
  • Trusted Firmware-M will be a new OSS project:
    • To reduce rework across our partners
    • To speed up device or component validation against standards such as Common Criteria EAL
  • Open to any RTOS and other partners

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Not answered what action will be performed by the master based on the read and write responce in axi 4?
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Suggested answer Modify SP register and PC register in Cortex-M1 using Keil
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0 votes 110 views 3 replies Latest 13 hours ago by 42Bastian Schick Answer this
Answered Where do I find presentations and photos from SC'18? Started 5 months ago by John Linford 0 replies 894 views
Not answered what action will be performed by the master based on the read and write responce in axi 4? Started 8 hours ago by Hem Patel 0 replies 20 views
Not answered Object detection Started 8 hours ago by Martin Peniak 0 replies 15 views
Suggested answer Cortex-A Support in MacOS Latest 8 hours ago by Ron Aaron 4 replies 466 views
Not answered Trigger a Software Interrupt Started 9 hours ago by Aquox 0 replies 14 views
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil Latest 13 hours ago by 42Bastian Schick 3 replies 110 views