Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables users to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm DS-5. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in Arm SoC Designer and certain models can also be used in SystemC simulation environments.

Swap & Play

Many Cycle Models support Swap & Play which enables a system to start running using a Fast Model representation and then switch to a Cycle Model representation at any breakpoint. This means a virtual prototype can boot an OS in a minute and then switch to a 100% accurate version to enable detailed debug and analysis. 

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72
Cortex-R Series Cortex-R4, Cortex-R5, Cortex-R7, Cortex-R8
Cortex-M Series Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, NIC-301, CCI-400, CCN-502, CCN-504, CCN-508
Interrupt Controllers GIC400, PL190, PL192, PL390
System Memory Management Units MMU-400
Memories DMC-400,PL340, PL341, PL351, PL352, PL353 and PL354

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

Learn more

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Answered Where do I find presentations and photos from SC'18? 0 votes 459 views 0 replies Started 2 months ago by John Linford Answer this
Discussion Please consider my tag for inclusion on the ARM Community
  • Community
1 votes 16633 views 25 replies Latest 1 months ago by SULMIYATDAD Answer this
Answered M0+ Stack Pointer (PSP/MSP) Clarification
  • Cortex-M0
  • R13 (SP Stack Pointer)
  • cortex-m0+
0 votes 645 views 15 replies Latest 12 hours ago by Sean Dunlevy Answer this
Suggested answer Why is PC-relative addressing deprecated for STR and VSTR in ARMv7-M4? 0 votes 86 views 2 replies Latest 12 hours ago by Dan Lewis Answer this
Not answered 3 questions on the KEIL usage
  • Keil MDK
  • Keil Tools
0 votes 14 views 0 replies Started 17 hours ago by hxxiao Answer this
Not answered DesignStart Cortex-M3 FPGA simulation with Cadence IES 0 votes 29 views 0 replies Started 20 hours ago by Stephan Answer this
Not answered DesignStart Eval on Terasic MAX10-Standard Board 0 votes 36 views 0 replies Started 23 hours ago by nash Answer this
Not answered What is meant by a Master in the AHB-Lite specification? 0 votes 26 views 0 replies Started yesterday by Kedhar Guhan Answer this
Not answered Is during AXI unaligned transfer not all WDATA bits used?
  • AXI
  • AXI4
0 votes 26 views 0 replies Started yesterday by hayk Answer this
Not answered Neoverse N1 CPU Questions 0 votes 115 views 0 replies Started yesterday by Riccardo89 Answer this
Not answered Fundamental Doubt in AHB Bus Architecture
  • Protocols
  • SoC Implementation
  • Interface Bus Architecture
  • Networking Protocol
  • ahb-lite
  • microcontroller
0 votes 56 views 0 replies Started yesterday by Kedhar Guhan Answer this
Suggested answer ASM strong function gets replaced by weak function 0 votes 107 views 1 replies Latest 2 days ago by Pavel Krupets Answer this
Answered Where do I find presentations and photos from SC'18? Started 2 months ago by John Linford 0 replies 459 views
Discussion Please consider my tag for inclusion on the ARM Community Latest 1 months ago by SULMIYATDAD 25 replies 16633 views
Answered M0+ Stack Pointer (PSP/MSP) Clarification Latest 12 hours ago by Sean Dunlevy 15 replies 645 views
Suggested answer Why is PC-relative addressing deprecated for STR and VSTR in ARMv7-M4? Latest 12 hours ago by Dan Lewis 2 replies 86 views
Not answered 3 questions on the KEIL usage Started 17 hours ago by hxxiao 0 replies 14 views
Not answered DesignStart Cortex-M3 FPGA simulation with Cadence IES Started 20 hours ago by Stephan 0 replies 29 views
Not answered DesignStart Eval on Terasic MAX10-Standard Board Started 23 hours ago by nash 0 replies 36 views
Not answered What is meant by a Master in the AHB-Lite specification? Started yesterday by Kedhar Guhan 0 replies 26 views
Not answered Is during AXI unaligned transfer not all WDATA bits used? Started yesterday by hayk 0 replies 26 views
Not answered Neoverse N1 CPU Questions Started yesterday by Riccardo89 0 replies 115 views
Not answered Fundamental Doubt in AHB Bus Architecture Started yesterday by Kedhar Guhan 0 replies 56 views
Suggested answer ASM strong function gets replaced by weak function Latest 2 days ago by Pavel Krupets 1 replies 107 views