Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables users to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm DS-5. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in Arm SoC Designer and certain models can also be used in SystemC simulation environments.

Swap & Play

Many Cycle Models support Swap & Play which enables a system to start running using a Fast Model representation and then switch to a Cycle Model representation at any breakpoint. This means a virtual prototype can boot an OS in a minute and then switch to a 100% accurate version to enable detailed debug and analysis. 

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72
Cortex-R Series Cortex-R4, Cortex-R5, Cortex-R7, Cortex-R8
Cortex-M Series Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, NIC-301, CCI-400, CCN-502, CCN-504, CCN-508
Interrupt Controllers GIC400, PL190, PL192, PL390
System Memory Management Units MMU-400
Memories DMC-400,PL340, PL341, PL351, PL352, PL353 and PL354

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

Learn more

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Forums

Answered Where do I find presentations and photos from SC'18? 0 votes 245 views 0 replies Started 1 months ago by John Linford Answer this
Discussion Please consider my tag for inclusion on the ARM Community 0 votes 15874 views 25 replies Latest 10 days ago by SULMIYATDAD Answer this
Suggested answer CANNOT ENTER INTO DEBUG MODE 0 votes 29 views 1 replies Latest 13 hours ago by Kevin Bernhardt Answer this
Suggested answer Mali-470 mp4 throughput? 0 votes 63 views 2 replies Latest 17 hours ago by Johnson554 Answer this
Suggested answer Why AXI4 changed the definition of AxCACHE?
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Suggested answer Whether Armv7-A has a Write Buffer 0 votes 156 views 7 replies Latest 21 hours ago by vstehle Answer this
Suggested answer Is ARM-NN compatible with CMSIS-NN
  • Neural Network
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Not answered Using GICv2 with FVP
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0 votes 41 views 0 replies Started yesterday by josecm Answer this
Suggested answer FastModels reset
  • DS-5 Debugger
  • Fast Models
0 votes 239 views 4 replies Latest yesterday by josecm Answer this
Suggested answer AXI read response in error case 0 votes 98 views 1 replies Latest yesterday by Colin Campbell Answer this
Answered dsb and dmb 0 votes 965 views 11 replies Latest 2 days ago by digital_kevin Answer this
Suggested answer Please, recommend a book to learn coding in assembly 0 votes 143 views 1 replies Latest 2 days ago by Juha Aaltonen Answer this
Answered Where do I find presentations and photos from SC'18? Started 1 months ago by John Linford 0 replies 245 views
Discussion Please consider my tag for inclusion on the ARM Community Latest 10 days ago by SULMIYATDAD 25 replies 15874 views
Suggested answer CANNOT ENTER INTO DEBUG MODE Latest 13 hours ago by Kevin Bernhardt 1 replies 29 views
Suggested answer Mali-470 mp4 throughput? Latest 17 hours ago by Johnson554 2 replies 63 views
Suggested answer Why AXI4 changed the definition of AxCACHE? Latest 20 hours ago by Colin Campbell 1 replies 82 views
Suggested answer Whether Armv7-A has a Write Buffer Latest 21 hours ago by vstehle 7 replies 156 views
Suggested answer Is ARM-NN compatible with CMSIS-NN Latest 23 hours ago by Tim Hartley 1 replies 41 views
Not answered Using GICv2 with FVP Started yesterday by josecm 0 replies 41 views
Suggested answer FastModels reset Latest yesterday by josecm 4 replies 239 views
Suggested answer AXI read response in error case Latest yesterday by Colin Campbell 1 replies 98 views
Answered dsb and dmb Latest 2 days ago by digital_kevin 11 replies 965 views
Suggested answer Please, recommend a book to learn coding in assembly Latest 2 days ago by Juha Aaltonen 1 replies 143 views