Performance Optimization with Cycle Models
Instrumented for Analysis
Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm DS-5. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.
Implementation level accuracy
Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in Arm SoC Designer and certain models can also be used in SystemC simulation environments.
Swap & Play
Many Cycle Models support Swap & Play which enables a system to start running using a Fast Model representation and then switch to a Cycle Model representation at any breakpoint. This means a virtual prototype can boot an OS in a minute and then switch to a 100% accurate version to enable detailed debug and analysis.
Creation of Arm Cycle Models
Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download
CPU and Subsystem Portfolio
Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.
CPU Cycle Models
|Cortex-A Series||Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72|
|Cortex-R Series||Cortex-R4, Cortex-R5, Cortex-R7, Cortex-R8|
|Cortex-M Series||Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4|
Faster Productivity with CPAKs
In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.
System IP Cycle Models
|Interconnect||NIC-400, NIC-301, CCI-400, CCN-502, CCN-504, CCN-508|
|Interrupt Controllers||GIC400, PL190, PL192, PL390|
|System Memory Management Units||MMU-400|
|Memories||DMC-400,PL340, PL341, PL351, PL352, PL353 and PL354
Cycle Models for DesignStart
Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.