Cycle Models | Cycle Model Studio

Generating a Component with Cycle Model Studio

Cycle Model Studio

In a modern system on chip design, as much as 80% of the design is existing intellectual property (IP), either re-used from previous projects or provided by a third party. Cycle Model Studio enables the user to leverage this IP, in all of its configurations, to jump start the creation of a complete, and accurate virtual prototype.

Automatically compiles RTL into high-speed software models
Straightforward GUI manages model creation and validation
Easy configuration management for model variants

Platform Integrations

It is important to be able to use your hardware models in your choice of system on chip verification environments. Cycle Model Studio was architected to support any system simulation environment. There is no need to develop unique models for each platform. Cycle Model Studio provides direct integration into the following verification environments:

Arm SoC Designer
All TLM-2.0 virtual prototype environments
All SystemC simulation environments
RTL simulation environments from Synopsys, Cadence and Mentor

One Model - Many Uses

Cycle Model Studio's many platform integrations mean that you have the versatility to use the Cycle Models in all of your development environments. Software engineers can focus on a "data-book" view of the device for programming. Architects have access to the buses, interfaces and transactions. Hardware engineers have full debug flexibility and visibility into the RTL including waveform dumping. Because the model is common, all of your teams can work on solving problems, instead of the error prone process of porting models across different verification environments.