A Safety Package is an Arm product that enables Arm IP to be used in safety-related systems for markets such as automotive, industrial, avionics and others. The Safety Package includes a set of documentation artifacts or evidence and any specific safety claims and results of certification activities that Arm holds for an individual IP. The documentation provides partners with information for the Arm IP in support of their safety argumentation and as evidence for safety assessors.
What does a Safety Package include?
Components of the Safety Package include:
A Safety Manual
This document provides:
- The overview of the product
- The specification of any fault detection and reporting mechanisms included with the IP
- The Assumptions of Use
- The results of the assessment activities
Safety analysis reports
- As a minimum, the Safety Package includes a detailed Failure Mode, Effects, and Diagnostic Analysis (FMEDA) for the IP. The FMEDA provides a clear view of the failure modes for the different IP subblocks, their effects at the IP boundaries, and the coverage achieved by any safety mechanisms included with the IP.
- In addition to the FMEDA a Dependent Failure Analysis (DFA) is provided as applicable. This document analyses the source of common cause failures in the IP and the mitigation that either Arm or the customer should implement to address identified common cause failures.
Development Interface Report (DIR)
Arm delivers a standardized agreement using the DIR with partners. The DIR clarifies the ISO 26262 activities that Arm takes responsibility for, and provides a full view of the standard activities, work products, and mapping. Arm provides this standardized DIR instead of a specific Development Interface Agreement (DIA) for distributed development in accordance with ISO 26262:2018.
What are the levels of Functional Safety support?
Arm defines three levels of functional safety support to our customers:
- Minimum level (Evaluation enablement product, ISO 26262 Part 8 Clause 13, or Route 3s IEC 61508 Part 3)
- Limited to certain legacy IP
- No Safety Package provided, only evaluation checklist (Table 31 ISO 26262 Part 11 and supporting processes) on request
- Aid the evaluation of the IP for the avoidance of systematic failures only
- Standard level (Evaluation enablement product, ISO 26262 Part 8 Clause 13, or Route 3s IEC 61508 Part 3)
- Applicable to some IP developed before 2018, see the Arm IP with Safety Packages table
- Safety Package is provided with all its components
- No independent assessment or certification is provided
- Extended level (SEooC with safety claims)
- Applicable to most and all future AE products, see the Arm IP with Safety Packages table
- Safety Package is provided with all its components
- ASIL and SIL claims on the avoidance of systematic faults and hardware metrics depending on the product
- Independently assessed and certified by a third-party assessor
Arm Software Test Libraries
Arm Software Test Libraries (STL) complement Arm functional safety technology. STLs are efficient assembly language routines that detect presence of permanent faults within a specific Arm processor. They are executed by the processor enabling self-testing of the IP at start-up and during application run time.
STLs are called through a C language Application Programmer Interface (API) enabling developers to quickly and easily schedule execution of the required tests. The STLs have been developed with a systematic development process aligned to ISO26262 ASIL D and IEC61508 SIL3. The STLs can be used to make a valuable contribution to Single Point Fault metrics, particularly in systems with ASIL B requirements.
Arm IP with Safety Packages
The Arm Safety Ready Portfolio consists of IP supported by safety packages and development tools and solutions to enable functional safety.
Development tools include:
- Software Test Libraries (STL)
- Functional Safety Run-Time System (FuSa RTS)
- Arm Compiler for Functional Safety.
| Processor | Available in Arm Flexible Access | Safety Documentation Package |
Software Test Library Support |
||
| Supported |
Level | ||||
| Cortex-A |
Cortex-A78AE |
No |
Yes |
Extended |
In development |
| Cortex-A76AE | No |
Yes |
Extended |
No |
|
| Cortex-A76 |
No | Yes |
Extended |
No |
|
| Cortex-A75 |
No |
Yes |
Standard | No |
|
| Cortex-A72 |
No |
Yes |
Standard |
Available in July 2021 |
|
| Cortex-A65AE |
No |
Yes |
Extended | No |
|
| Cortex-A65 |
No |
Yes |
Extended |
No |
|
| Cortex-A55 |
No |
Yes |
Extended |
No |
|
| Cortex-A53 |
Yes |
Yes |
Standard |
Yes |
|
| Cortex-A35 |
Yes | Yes |
Standard |
No |
|
| Cortex-A34 |
Yes |
Yes |
Standard |
No |
|
| Cortex-A32 |
Yes |
Yes |
Standard |
No |
|
| Cortex-A7 |
Yes |
No |
- |
No |
|
| Cortex-A5 |
Yes |
No |
- |
No |
|
| Cortex-R |
Cortex-R52+ |
No |
Yes |
Extended |
In development |
| Cortex-R52 | Yes |
Yes |
Extended |
Yes |
|
| Cortex-R8 |
Yes | No |
- |
No |
|
| Cortex-R7 |
Yes |
No |
- |
No | |
| Cortex-R5 |
Yes |
Yes |
Extended |
Yes | |
| Cortex-R4 |
Yes |
No |
- |
No |
|
| Cortex-M |
Cortex-M55 | Yes |
Yes |
Extended |
Available in 2022 |
| Cortex-M35P |
No |
No |
- |
No |
|
| Cortex-M33 | Yes |
Yes |
Extended |
Yes | |
| Cortex-M23 | Yes | Yes | Extended |
No |
|
| Cortex-M7 | Yes | Yes |
Standard |
No |
|
| Cortex-M4 | Yes | Yes |
Standard | Yes |
|
| Cortex-M3 | Yes |
Yes |
Standard |
Yes |
|
| Cortex-M1 | Yes |
No |
- |
No |
|
| Cortex-M0+ | Yes |
Yes |
Standard |
Yes |
|
| Cortex-M0 | Yes |
No |
- |
No |
|
| GPU |
Mali-G78AE | No | Yes | Extended | N/A |
| Mali-G76 | No |
No |
- |
N/A |
|
| Mali-G52 |
Yes |
No |
- |
N/A |
|
| ISP |
Mali-C71AE |
No |
Yes |
Extended |
N/A |
| System |
GIC-600AE |
No |
Yes |
Extended |
N/A |
| MMU-600AE |
No |
Yes |
Extended |
N/A | |
| CMN-600AE |
No | Yes |
Extended |
N/A |
|