Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.

Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A75, Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5
Cortex-M Series Cortex-M33, Cortex-M23, Cortex-M7, Cortex-M3, Cortex-M0+

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Free White Papers

Cortex A53 System Optimization »

Software Driven Power Analysis »

Modeling Techniques Maximize Value of Virtual Platforms »

More Resources

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

Learn more

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Community Blogs

Blog post image
HPC highlights from the Arm Research Summit

Read about the highlights from the Arm research summit including birds of a feather sessions and presentations.

2 days ago by Roxana
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Arm Research Summit 2019: Catch Up and Highlights

The fourth annual Arm Research Summit, and the first in the US, held in Austin, Texas, created a collaborative space for academics, researchers and industry experts globally to discuss complex computing challenges in the future landscape.

3 days ago by Rhiannon Burleigh
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Vulkan Mobile Best Practice: Picking the Most Efficient Load/Store Operatio

A detailed best practice guide to setting up LOAD and STORE options when using the Vulkan Best Practices tutorials from Arm.

5 days ago by Attilio Provenzano
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AMBA moves forward with major revisions to AXI and CHI specifications

This blog covers major revisions to two key AMBA specifications - the AMBA AXI and ACE Protocol Specification Issue G and the AMBA CHI Architecture Specification Issue D.

5 days ago by Francisco Socal
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The ICs of 2030

This blog is a companion to my keynote at Arm TechCon on 10 October, 2019.  I am publishing a blog form because I cover a LOT of ground in that 20 minute talk, and there are i

10 days ago by Greg Yeric
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Taming of the Edge

Read how organizations are capturing the value of IoT, by re-evaluating solution strategies.

11 days ago by Augustine Nebu Philips

Community Forums

Answered Zero Copy Buffer Allocation on Arm Mali MidGard GPUs Opencl1.2
  • Midgard
  • OpenCL
  • C++
  • Mali OpenCL SDK
  • gpu
 0 votes 4420 views 4 replies Latest yesterday by abhi.verma Answer this
Answered Marketplace doesn't work 0 votes 417 views 2 replies Latest 3 days ago by Arek Answer this
Answered Setting PC for and waking up secondary cores from the primary core
  • Armv8-A
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Answered Unaligned accesses - CMSDK Example Cortex M0
  • Cortex-M0
 0 votes 671 views 8 replies Latest 6 days ago by eugch Answer this
Answered Why ARM does not support 64bit for faulting address of IPA?
  • ARMv8 Exception Model
  • Armv8-A
 0 votes 247 views 1 replies Latest 6 days ago by 42Bastian Schick Answer this
Answered arm-none-eabi-ld for binary generation 0 votes 233 views 1 replies Latest 6 days ago by Joey Ye Answer this
Answered Zero Copy Buffer Allocation on Arm Mali MidGard GPUs Opencl1.2 Latest yesterday by abhi.verma 4 replies 4420 views
Answered Marketplace doesn't work Latest 3 days ago by Arek 2 replies 417 views
Answered Setting PC for and waking up secondary cores from the primary core Latest 4 days ago by jhoney 12 replies 5740 views
Answered Unaligned accesses - CMSDK Example Cortex M0 Latest 6 days ago by eugch 8 replies 671 views
Answered Why ARM does not support 64bit for faulting address of IPA? Latest 6 days ago by 42Bastian Schick 1 replies 247 views
Answered arm-none-eabi-ld for binary generation Latest 6 days ago by Joey Ye 1 replies 233 views