Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.

Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A75, Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5
Cortex-M Series Cortex-M33, Cortex-M23, Cortex-M7, Cortex-M3, Cortex-M0+

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Free White Papers

Cortex A53 System Optimization »

Software Driven Power Analysis »

Modeling Techniques Maximize Value of Virtual Platforms »

More Resources

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Community Blogs

Blog post image
Vulkan Best Practices - Memory limits with Vulkan on Mali GPUs

This article covers situations in which a Vulkan application might trigger an out of memory (OOM) condition on Mali GPUs, resulting in a DEVICE_LOST error, even if the API usage is correct.

9 hours ago by Attilio Provenzano
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Collaboration Case Study: Machine Learning Hardware with Harvard University

University engagements play a significant role in our partnerships at Arm Research, helping us extend our reach and build understanding of technologies as they emerge. Harvard University is one of those partners, collaborating with us on Machine…

yesterday by Paul Whatmough
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Beyond traditional ATPG: A test methodology targeting in-cell defects

Read about the goal of silicon testing and how success is measured in defective-parts-per-million (DPPM).

4 days ago by Rupal Gandhi
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Reduce TCO with Arm Based SmartNICs

Read about the details of SmartNICs and how they are used to offload processing that is done by server CPUs.

5 days ago by Julio Suarez
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让数值算法在Arm edge端跑的更快

CMSIS DSP 库作为高度优化的嵌入式系统数字信号计算库一直以来深受广大开发者所喜爱，随着人工智能(Artificial Intelligence )逐步向Edge端扩展，Edge端的数字计算负载也越来越大，为了缓解计算的压力，各种框架也在Edge端采用CMSIS DSP库进行优化加速。科学计算环境和嵌入式开发环境有很大的区别，比如科学计算往往采用Python，SCIPy，Matlab,而这些环境一般是无法在低功耗嵌入式环境，特别是MCU，下运行。由于目的不同，二者之间的使用方法也存在一些差

6 days ago by 章政
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Vulkan Mobile Best Practices - Descriptor and Buffer Management

Read about the options to improve both descriptor and buffer management when developing on Mobile with the Vulkan API.

7 days ago by Attilio Provenzano

Community Forums

Answered Difference btw AXI3 and AXI4
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Answered Token-pasting ("##") with armcc 5.06
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Answered DS-5 5.29.0 on Windows 10 1803 0 votes 6025 views 5 replies Latest 2 days ago by Khan Saab Answer this
Answered Android NDK options: What compiler flags should I use for my libraries and apps to get the best performance across the widest range of SoCs?
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Answered hardfault error
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Answered Difference btw AXI3 and AXI4 Latest 8 hours ago by Colin Campbell 6 replies 10789 views
Answered WID not present in AXI4 Latest 9 hours ago by Colin Campbell 1 replies 162 views
Answered Token-pasting ("##") with armcc 5.06 Latest yesterday by Brandon Price 2 replies 213 views
Answered DS-5 5.29.0 on Windows 10 1803 Latest 2 days ago by Khan Saab 5 replies 6025 views
Answered Android NDK options: What compiler flags should I use for my libraries and apps to get the best performance across the widest range of SoCs? Latest 4 days ago by iosman000 2 replies 4724 views
Answered hardfault error Latest 4 days ago by 42Bastian Schick 4 replies 963 views