Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.

Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

Get started with Cortex-M55 today within a familiar Cortex-M development environment

Compare performance, learn new instructions and optimize code with single programmer’s model for DSP/ML workloads.

More about Arm tools for Cortex-M55

CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A75, Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5
Cortex-M Series Cortex-M0+, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M55

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Free White Papers

Cortex A53 System Optimization »

Software Driven Power Analysis »

Modeling Techniques Maximize Value of Virtual Platforms »

More Resources

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

Learn more

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Community Blogs

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Why IoT is changing the face of manufacturing

In this blog, read about the changes in Internet of Things (IoT) manufacturing.

yesterday by Rob Turner
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M0N0: An Arm Research platform for N-ZERO sensors

Changing the batteries: A routine task just about manageable if it is needed once a month on household devices. But what if your devices are deployed in their thousands in remote, inaccessible locations?

yesterday by Pranay Prabhat
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Super Resolution on Arm NPU

Read about super resolution on Arm NPU, content written by Alex Shang, Yabin Zheng, Mary Bennion, and Alex Avramenko. Background In the consumer electronics industry, high resolution has become widespread and is an expected feature that provides…

6 days ago by Alex Avramenko
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Delivering security ‘defense in depth’ through Total Compute

This blog explains how Total Compute will offer security protections, not only on consumer devices but across the entire ecosystem.

7 days ago by Ian Smythe
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The Great Shift Left: Pre-silicon development solutions from Arm and Cadenc

In this blog, read about how Arm and Cadence are using virtual prototyping in pre-silicon development solutions.

7 days ago by Ronan Synnott
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Training DNN IoT Applications for Deployment on Analog NVM Crossbars

At the heart of computing at the edge, we find efficient low-power signal processors and ML accelerators. However, limits on compute and memory resources restrict the size and the complexity of the ML models deployable.

8 days ago by Fernando García Redondo

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Answered Inconsistent shareability domain on tlbi instructions
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Answered Understanding interrupt latency and jitter in Cortex-M
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Answered Problems with setting up the event recorder for LPC1769
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 0 votes 975 views 11 replies Latest 4 days ago by coldspark Answer this
Answered Inconsistent shareability domain on tlbi instructions Latest 3 days ago by josecm 3 replies 530 views
Answered how to calculate unaligned address for APB? Latest 3 days ago by Colin Campbell 8 replies 11027 views
Answered What does this message mean? osRtxInfo not found Latest 4 days ago by Adam Lins 3 replies 456 views
Answered Understanding interrupt latency and jitter in Cortex-M Latest 4 days ago by 42Bastian Schick 7 replies 1006 views
Answered Updating my avatar Latest 4 days ago by Jerome Decamps - 杜尚杰 2 replies 443 views
Answered Problems with setting up the event recorder for LPC1769 Latest 4 days ago by coldspark 11 replies 975 views