Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.

Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

Get started with Cortex-M55 today within a familiar Cortex-M development environment

Compare performance, learn new instructions and optimize code with single programmer’s model for DSP/ML workloads.

More about Arm tools for Cortex-M55

CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A75, Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5
Cortex-M Series Cortex-M0+, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M55

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Free White Papers

Cortex A53 System Optimization »

Software Driven Power Analysis »

Modeling Techniques Maximize Value of Virtual Platforms »

More Resources

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Community Forums

Answered If I don't see any events in the EvenRecorder other than the initialization, does it mean that the RTOS is not running?
  • uVision
 0 votes 243 views 2 replies Latest 11 hours ago by coldspark Answer this
Answered Locating large data blocks in LPC4078 SRAM 0 votes 265 views 2 replies Latest 22 hours ago by TdeP Answer this
Answered Speculative execution/loads on Cortex-A5
  • Cortex-A5
  • Pipeline Control and Execution
  • Cache
 0 votes 1223 views 5 replies Latest yesterday by vstehle Answer this
Answered Inconsistent shareability domain on tlbi instructions
  • Cortex-A72
  • Cortex-A53
 0 votes 566 views 3 replies Latest 4 days ago by josecm Answer this
Answered how to calculate unaligned address for APB? 0 votes 11070 views 8 replies Latest 4 days ago by Colin Campbell Answer this
Answered What does this message mean? osRtxInfo not found
  • uVision
 0 votes 474 views 3 replies Latest 5 days ago by Adam Lins Answer this
Answered If I don't see any events in the EvenRecorder other than the initialization, does it mean that the RTOS is not running? Latest 11 hours ago by coldspark 2 replies 243 views
Answered Locating large data blocks in LPC4078 SRAM Latest 22 hours ago by TdeP 2 replies 265 views
Answered Speculative execution/loads on Cortex-A5 Latest yesterday by vstehle 5 replies 1223 views
Answered Inconsistent shareability domain on tlbi instructions Latest 4 days ago by josecm 3 replies 566 views
Answered how to calculate unaligned address for APB? Latest 4 days ago by Colin Campbell 8 replies 11070 views
Answered What does this message mean? osRtxInfo not found Latest 5 days ago by Adam Lins 3 replies 474 views