Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

Get started with Cortex-M55 today within a familiar Cortex-M development environment

Compare performance, learn new instructions and optimize code with single programmer’s model for DSP/ML workloads.

More about Arm tools for Cortex-M55


CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Answered Inconsistent shareability domain on tlbi instructions
  • Cortex-A72
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0 votes 530 views 3 replies Latest 3 days ago by josecm Answer this
Answered how to calculate unaligned address for APB? 0 votes 11027 views 8 replies Latest 3 days ago by Colin Campbell Answer this
Answered What does this message mean? osRtxInfo not found
  • uVision
0 votes 456 views 3 replies Latest 4 days ago by Adam Lins Answer this
Answered Understanding interrupt latency and jitter in Cortex-M
  • Interrupt Handling
  • Cortex-M7
  • Cortex-M
  • Interrupt
0 votes 1006 views 7 replies Latest 4 days ago by 42Bastian Schick Answer this
Answered Updating my avatar 0 votes 443 views 2 replies Latest 4 days ago by Jerome Decamps - 杜尚杰 Answer this
Answered Problems with setting up the event recorder for LPC1769
  • Cortex-M
  • event
0 votes 975 views 11 replies Latest 4 days ago by coldspark Answer this
Answered Inconsistent shareability domain on tlbi instructions Latest 3 days ago by josecm 3 replies 530 views
Answered how to calculate unaligned address for APB? Latest 3 days ago by Colin Campbell 8 replies 11027 views
Answered What does this message mean? osRtxInfo not found Latest 4 days ago by Adam Lins 3 replies 456 views
Answered Understanding interrupt latency and jitter in Cortex-M Latest 4 days ago by 42Bastian Schick 7 replies 1006 views
Answered Updating my avatar Latest 4 days ago by Jerome Decamps - 杜尚杰 2 replies 443 views
Answered Problems with setting up the event recorder for LPC1769 Latest 4 days ago by coldspark 11 replies 975 views