Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

Arm DevSummit: designed for hardware and software engineers

Join Arm and its ecosystem partners to explore the latest advancements in computing for helping engineers designing and building integrated solutions. In 2020, deep-dive workshops and technical sessions will be held in an immersive virtual forum.

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CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A75, Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5, Cortex-R82*
Cortex-M Series Cortex-M0+, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M55

*Contact us to get access to these models prior to public release.

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

Learn more

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Answered How to make Ethos-U NPU work on an ARM Cortex-A + Cortex-M processor? 0 votes 1819 views 13 replies Latest 4 days ago by Kristofer Jonsson Answer this
Answered Keil MDK5 HTTP server - form input names Latest 3 days ago by Murilo Machado 3 replies 510 views
Answered reliability of Arm processors Latest 4 days ago by fixxxer 1 replies 258 views
Answered TLB stage2 translation Latest 4 days ago by fixxxer 1 replies 169 views
Answered How do I get the G72 userspace driver for Linux system Latest 4 days ago by fixxxer 2 replies 637 views
Answered Session resources from the Linaro Tech Days (virtual event) Latest 4 days ago by fixxxer 1 replies 743 views
Answered How to make Ethos-U NPU work on an ARM Cortex-A + Cortex-M processor? Latest 4 days ago by Kristofer Jonsson 13 replies 1819 views