Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

Get started with Cortex-M55 today within a familiar Cortex-M development environment

Compare performance, learn new instructions and optimize code with single programmer’s model for DSP/ML workloads.

More about Arm tools for Cortex-M55


CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Answered Fault Injection in ROM. 0 votes 389 views 6 replies Latest 8 hours ago by Broeker Answer this
Answered File 'pthread.h' not included in keil 0 votes 235 views 4 replies Latest yesterday by MHansra Answer this
Answered Cortex M0+, AHB state during Exception
  • Cortex-M0+
  • AHB
0 votes 96 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Answered cortex m7 STR fail 0 votes 294 views 6 replies Latest 3 days ago by 42Bastian Schick Answer this
Answered Invalid Exception Class
  • Cortex-A53
  • AArch64
0 votes 1725 views 2 replies Latest 5 days ago by Killbox Answer this
Answered Normal Memory ordering & precise state question 0 votes 1597 views 3 replies Latest 5 days ago by ianl Answer this
Answered Fault Injection in ROM. Latest 8 hours ago by Broeker 6 replies 389 views
Answered File 'pthread.h' not included in keil Latest yesterday by MHansra 4 replies 235 views
Answered Cortex M0+, AHB state during Exception Latest yesterday by 42Bastian Schick 1 replies 96 views
Answered cortex m7 STR fail Latest 3 days ago by 42Bastian Schick 6 replies 294 views
Answered Invalid Exception Class Latest 5 days ago by Killbox 2 replies 1725 views
Answered Normal Memory ordering & precise state question Latest 5 days ago by ianl 3 replies 1597 views