Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

Get started with Cortex-M55 today within a familiar Cortex-M development environment

Compare performance, learn new instructions and optimize code with single programmer’s model for DSP/ML workloads.

More about Arm tools for Cortex-M55


CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Answered which kind of code is calling the microlib of __aeabi_uread4(uread4)
  • Arm Compiler 5
0 votes 197 views 2 replies Latest 8 hours ago by Wei Jetim. Zhao Answer this
Answered ID issue 0 votes 467 views 2 replies Latest 19 hours ago by Colin Campbell Answer this
Answered Event Recorder with STM32F0
  • Cortex-M0
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0 votes 1533 views 8 replies Latest 22 hours ago by NSharp Answer this
Answered Analyzing optimized SPIR-V binaries using Mali Offline Compiler
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Answered Implementing a non-hanging USB listener 0 votes 2333 views 30 replies Latest 2 days ago by Kev Answer this
Answered Why does the printf debug only print weird symbols?
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0 votes 1114 views 16 replies Latest 5 days ago by coldspark Answer this
Answered which kind of code is calling the microlib of __aeabi_uread4(uread4) Latest 8 hours ago by Wei Jetim. Zhao 2 replies 197 views
Answered ID issue Latest 19 hours ago by Colin Campbell 2 replies 467 views
Answered Event Recorder with STM32F0 Latest 22 hours ago by NSharp 8 replies 1533 views
Answered Analyzing optimized SPIR-V binaries using Mali Offline Compiler Latest 2 days ago by speedym 4 replies 348 views
Answered Implementing a non-hanging USB listener Latest 2 days ago by Kev 30 replies 2333 views
Answered Why does the printf debug only print weird symbols? Latest 5 days ago by coldspark 16 replies 1114 views