Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.

Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5, Cortex-R82*
Cortex-M Series Cortex-M0+, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M55

*Contact us to get access to these models prior to public release.

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CCI-550, CCI-500
Interrupt Controllers GIC-600, GIC-500
Memories BP-140

Free White Papers

Cortex A53 System Optimization »

Software Driven Power Analysis »

Modeling Techniques Maximize Value of Virtual Platforms »

More Resources

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Community Blogs

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PlasticArm: Realizing the full potential of the Internet of Things

PlasticArm is bringing the possibility of seamlessly embedding billions of extremely low-cost, ultra-thin, conformable microprocessors into everyday objects – a significant leap forward in realising the Internet of Everything.

5 days ago by Charlotte Christopherson
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Gain up to 35% performance benefits for deploying Redis on AWS Graviton2

In this blog we compare the performance of Redis on Arm-based AWS Graviton2 processors to Intel Xeon processors.

6 days ago by Pranay Bakre
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Buried interconnects for signal routing

Buried interconnects can help mitigate the interconnect resistance issue and augment the technology scaling roadmap for sub-5nm process nodes.

10 days ago by Rahul Mathur
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Arm机密计算架构技术白皮书

作者：Arm 首席应用工程师 David Brooke 原文：https://developer.arm.com/documentation/den0125/0100 1.      概述 在本篇文章中，我们将介绍机密计算（Confidential Computing）在现代计算平台中扮演的角色，并解释机密计算的原理。然后我们将说明 Arm 机密计算架构 (Arm CCA) 如何在 Arm 计算平台中实现机密计算。 看完本文后，您将能够： 定义

10 days ago by Zenon Xiu (修志龙）
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The journey to a brave new world of secure, easy to deploy and maintain…

The first SystemReady IR product, the NXP i.MX 8M Mini EVK has been certified, leading the charge towards a consistent and best-in-class cloud native experience at the IoT edge.

12 days ago by Olivier Bernard
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Introducing the Scalable Matrix Extension for the Armv9-A Architecture

In this blog, read the details for Scalable Matrix Extension (SME). This is a new extension from the latest Arm Vision day announcement for Armv9-A.

12 days ago by Martin Weidmann

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Answered Where should I ask my question? Latest 2 months ago by Andy Neil 5 replies 7983 views
Answered STM32 UART DMA can receive first time correct then it receive nothing Latest 3 days ago by neo_hoang 4 replies 4458 views
Answered AXI4 - Data before address - why? Latest 4 days ago by af_23 6 replies 306 views
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) Latest 4 days ago by Colin Campbell 1 replies 215 views
Answered uVision 5.29.0.0 crashes when opening the debugger Latest 4 days ago by MTC 1 replies 210 views
Answered Is __CC_ARM not defined in the MDK Eval Version? Latest 5 days ago by Grant B 12 replies 776 views