Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

Get started with Cortex-M55 today within a familiar Cortex-M development environment

Compare performance, learn new instructions and optimize code with single programmer’s model for DSP/ML workloads.

More about Arm tools for Cortex-M55


CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A75, Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5
Cortex-M Series Cortex-M33, Cortex-M23, Cortex-M7, Cortex-M3, Cortex-M0+

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Answered Where can I find more information regarding CI/CD support for AArch64? 0 votes 519 views 6 replies Latest 12 hours ago by Kushal Koolwal Answer this
Answered Non-secure configuration of UART1 on Arm Musca-A1
  • Musca-A
  • TrustZone for Armv8-M
0 votes 332 views 4 replies Latest yesterday by Daniel Oliveira Answer this
Answered Arm64 Long Format Translation Table Walk
  • Memory Management Unit (MMU)
  • Arm64
0 votes 221 views 2 replies Latest yesterday by angeld Answer this
Answered timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR)
  • CoreSight Architecture
  • Cortex-M
  • Debugging
  • CoreSight
  • Cortex-M4
0 votes 350 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Answered what's the name of this electronic component? 0 votes 1287 views 3 replies Latest yesterday by Dean03 Answer this
Answered Cortex M0 - Returning from Interrupt
  • Cortex-M0
  • Arm Education Media
0 votes 1560 views 13 replies Latest 3 days ago by Mezan1 Answer this
Answered Where can I find more information regarding CI/CD support for AArch64? Latest 12 hours ago by Kushal Koolwal 6 replies 519 views
Answered Non-secure configuration of UART1 on Arm Musca-A1 Latest yesterday by Daniel Oliveira 4 replies 332 views
Answered Arm64 Long Format Translation Table Walk Latest yesterday by angeld 2 replies 221 views
Answered timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR) Latest yesterday by 42Bastian Schick 1 replies 350 views
Answered what's the name of this electronic component? Latest yesterday by Dean03 3 replies 1287 views
Answered Cortex M0 - Returning from Interrupt Latest 3 days ago by Mezan1 13 replies 1560 views