Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

Get started with Cortex-M55 today within a familiar Cortex-M development environment

Compare performance, learn new instructions and optimize code with single programmer’s model for DSP/ML workloads.

More about Arm tools for Cortex-M55


CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A75, Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5
Cortex-M Series Cortex-M33, Cortex-M23, Cortex-M7, Cortex-M3, Cortex-M0+

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Answered M4 Deep Sleep
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0 votes 236 views 2 replies Latest 19 hours ago by AliRizaDenenPezevenk Answer this
Answered GPU & High-Performance Computing $100K Research Challenge 0 votes 3151 views 4 replies Latest 2 days ago by John Linford Answer this
Answered Does MSR DAIF require ISB instruction? If no, why?
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  • Armv8-A
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Answered STM32F413ZG Program Size - code, RO-data,RW-data,ZI-data 0 votes 569 views 4 replies Latest 3 days ago by June Zhou Answer this
Answered FMC problem on GD32E103 0 votes 371 views 2 replies Latest 3 days ago by JosepI Answer this
Answered LPC55S69:CMSIS-DAP - ARMv8-M Error 0 votes 603 views 4 replies Latest 4 days ago by hzt_ Answer this
Answered M4 Deep Sleep Latest 19 hours ago by AliRizaDenenPezevenk 2 replies 236 views
Answered GPU & High-Performance Computing $100K Research Challenge Latest 2 days ago by John Linford 4 replies 3151 views
Answered Does MSR DAIF require ISB instruction? If no, why? Latest 3 days ago by scopichmu 2 replies 420 views
Answered STM32F413ZG Program Size - code, RO-data,RW-data,ZI-data Latest 3 days ago by June Zhou 4 replies 569 views
Answered FMC problem on GD32E103 Latest 3 days ago by JosepI 2 replies 371 views
Answered LPC55S69:CMSIS-DAP - ARMv8-M Error Latest 4 days ago by hzt_ 4 replies 603 views