Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.

Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A75, Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5
Cortex-M Series Cortex-M33, Cortex-M23, Cortex-M7, Cortex-M3, Cortex-M0+

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Free White Papers

Cortex A53 System Optimization »

Software Driven Power Analysis »

Modeling Techniques Maximize Value of Virtual Platforms »

More Resources

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

Learn more

Get support

Community Blogs

Blog post image
New Arm Mali-D37 DPU: rich display features in the smallest area possible…

Read about the new Arm Mali-D37 DPU, its key benefits and features.

16 hours ago by Sinan Yalcin
Blog post image
New Arm Mali-G57 GPU: bringing high-fidelity gaming and immersive…

Blog explores the features of the brand new Arm Mali-G57 GPU for mainstream smartphones and home appliances

16 hours ago by Daniele Di Donato
Blog post image
Optimizing AI workloads with Ethos NPUs

The new Ethos-N NPU series addresses the performance needs of the most demanding ML use cases to deliver a superlative UX without compromising battery life.

16 hours ago by Dylan Zika
Blog post image
Vulkan Mobile Best Practice - Appropriate Use of Surface Rotation

Surface rotation is an issue you have likely never heard before Vulkan – or even until now. This best practice guide brings you through all you need to know about surface rotation on mobile.

yesterday by Attilio Provenzano
Blog post image
Arm on Arm: Cadence Characterization in the AWS Cloud

Read about the explosion of new use cases across numerous businesses and areas of research and how Cadence characterizes the AWS cloud.

3 days ago by Darren Cepulis
Blog post image
HPC highlights from the Arm Research Summit

Read about the highlights from the Arm research summit including birds of a feather sessions and presentations.

5 days ago by Roxana Rusitoru

Community Forums

Answered Zero Copy Buffers using cl_arm_import_memory extension in OpenCL 1.2 - arm mali midgard GPUs.
  • Midgard
  • Mali GPU (Midgard Architecture)
  • Mali OpenCL SDK
 0 votes 1345 views 7 replies Latest 8 hours ago by Kévin Petit Answer this
Answered interfacing m66 gsm module with stm32f0 0 votes 325 views 2 replies Latest 14 hours ago by Rishabh_sharma Answer this
Answered STM32L4xxx and RTOSv1/. Sending two signals from one ISR at the same time, to the same thread, results in abnormal behavior. 0 votes 1061 views 9 replies Latest yesterday by Sergey Gerasimenko Answer this
Answered Irregular behaviour of vectors in OpenCL(1.2) kernels
  • OpenCL
  • Mali GPU (Midgard Architecture)
  • Mali OpenCL SDK
  • Linux OpenCL
 0 votes 5825 views 1 replies Latest 2 days ago by Kévin Petit Answer this
Answered AXI4:- Unaligned transfer 0 votes 1084 views 3 replies Latest 2 days ago by Colin Campbell Answer this
Answered Map/Unmap operations with Zero copy buffer.
  • OpenCL
  • High-Performance Computing (HPC)
  • Mali GPU (Midgard Architecture)
 0 votes 3035 views 1 replies Latest 2 days ago by Kévin Petit Answer this
Answered Zero Copy Buffers using cl_arm_import_memory extension in OpenCL 1.2 - arm mali midgard GPUs. Latest 8 hours ago by Kévin Petit 7 replies 1345 views
Answered interfacing m66 gsm module with stm32f0 Latest 14 hours ago by Rishabh_sharma 2 replies 325 views
Answered STM32L4xxx and RTOSv1/. Sending two signals from one ISR at the same time, to the same thread, results in abnormal behavior. Latest yesterday by Sergey Gerasimenko 9 replies 1061 views
Answered Irregular behaviour of vectors in OpenCL(1.2) kernels Latest 2 days ago by Kévin Petit 1 replies 5825 views
Answered AXI4:- Unaligned transfer Latest 2 days ago by Colin Campbell 3 replies 1084 views
Answered Map/Unmap operations with Zero copy buffer. Latest 2 days ago by Kévin Petit 1 replies 3035 views