Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.

Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5, Cortex-R82*
Cortex-M Series Cortex-M0+, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M55

*Contact us to get access to these models prior to public release.

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CCI-550, CCI-500
Interrupt Controllers GIC-600, GIC-500
Memories BP-140

Free White Papers

Cortex A53 System Optimization »

Software Driven Power Analysis »

Modeling Techniques Maximize Value of Virtual Platforms »

More Resources

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Community Blogs

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AArch64 Docker images for TensorFlow and PyTorch

Docker images for TensorFlow and PyTorch running on Ubuntu for the Arm architecture are now available. This article explains where to get the container images, how to run them, and the instructions to build them yourself.

19 hours ago by Jason Andrews
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TensorFlow and PyTorch container monthly releases by Arm

Arm is now releasing PyTorch and TensorFlow container images monthly. In this blog, let us look at what is available in our 21.04 release and what is coming in the future.

21 hours ago by Ashok Bhat
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Getting ready for SVE with GCC 11

The GCC compiler can use the Scalable Vector Extension SVE in a number of ways, from auto-vectorization to C and C++ intrinsics. We explain how to make the most of SVE in your GCC-compiled application

yesterday by Kyrylo Tkachov
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Introducing interleave-batched linear algebra functions in Arm PL

This blog introduces "interleave-batch" functions in Arm Performance Libraries, targeted at solving large batches of small problems in linear algebra.

2 days ago by Chris Armstrong
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Experiences in teaching Arm-based courses: A blended approach

In this blog, we revisit our first co-certified course on “Rapid Embedded Systems Design and Programming” with Nanyang Polytechnic.

3 days ago by Robert Iannello
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VR Best Practices for Game Development

Andrew Connell from 'VR with Andrew' goes through some really handy tips and tricks for VR game development that can take your VR game to the next level.

3 days ago by Jayant Roy

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Answered cortex a53 : How to detect cached data is invalid ? (use ddr memory) Latest 20 hours ago by Nickpalmer 5 replies 803 views
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