Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download


CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

CPU Cycle Models


Arm IP Exchange

CPU Family Processor
Cortex-A Series Cortex-A55, Cortex-A53, Cortex-A35, Cortex-A32
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R5, Cortex-R82*
Cortex-M Series Cortex-M0+, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M55

*Contact us to get access to these models prior to public release.

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400CCI-550CCI-500
Interrupt Controllers GIC-600, GIC-500
Memories BP-140

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Community Forums

Answered Where should I ask my question?
  • ARM Community
0 votes 7208 views 5 replies Latest 19 days ago by Andy Neil Answer this
Answered EMBEDDED C - Volatile qualifier does not matter in my interrupt routine
  • Cortex-M7
  • stm32 h7
0 votes 38 views 4 replies Latest 8 hours ago by mingche_joe Answer this
Answered Custom bootable image 0 votes 94 views 2 replies Latest 9 hours ago by segfault Answer this
Answered Failed to load "<project>.axf" - ERROR (CMD16-TAD274-NAL22) - Can't run bare-metal application from SDRAM.
  • Arm Development Studio
  • SoC FPGA
  • Baremetal
0 votes 610 views 5 replies Latest 2 days ago by elliots Answer this
Answered MULSHIFT32 in 14 cycles 0 votes 569 views 10 replies Latest 2 days ago by 42Bastian Schick Answer this
Answered In ARM7 and ARM9 PC=current + 8, but in the cortex-A7(8-stage pipeline) the PC is also the same value(PC=current +8), how does this work?
  • Arm7
  • Arm9
  • Armv8-A
  • Cortex-A
  • Cortex-A7
0 votes 3775 views 3 replies Latest 2 days ago by Takahashi842 Answer this
Answered Where should I ask my question? Latest 19 days ago by Andy Neil 5 replies 7208 views
Answered EMBEDDED C - Volatile qualifier does not matter in my interrupt routine Latest 8 hours ago by mingche_joe 4 replies 38 views
Answered Custom bootable image Latest 9 hours ago by segfault 2 replies 94 views
Answered Failed to load "<project>.axf" - ERROR (CMD16-TAD274-NAL22) - Can't run bare-metal application from SDRAM. Latest 2 days ago by elliots 5 replies 610 views
Answered MULSHIFT32 in 14 cycles Latest 2 days ago by 42Bastian Schick 10 replies 569 views
Answered In ARM7 and ARM9 PC=current + 8, but in the cortex-A7(8-stage pipeline) the PC is also the same value(PC=current +8), how does this work? Latest 2 days ago by Takahashi842 3 replies 3775 views