Get started on Arm
Our Research Enablement Kits are designed to help researchers get the most out of widely available Arm technologies, including DesignStart IP and the gem5 open source simulator. They include software packages, models, hardware prototypes, and services to help universities worldwide harness Arm and partner-based technologies and solutions as efficiently as possible. Research Enablement Kits provide:
- Quick and simple access to Arm and partner-based IP and technologies
- High quality research materials and packages
- Detailed documentation and whitepapers
Explore the table below for more information on what is available. If you are looking for access to other IP, please contact us.
|Kit name||System modeling using gem5||SoC design and prototyping||ASAP7|
|Overview||This kit will guide you through Arm-based system modeling using the gem5 simulator and a 64-bit processor model based on Armv8-A.||This kit will help you design and prototype a SoC based on the Arm Cortex-M0 CPU.||This is a set of high-quality SC libraries for the ASAP7 predictive process design kit.|
|Why use?||gem5 is a well-known sophisticated simulator used for computer system research at both architecture and micro-architecture levels. It is capable of modeling several ISAs, and does so with enough details such that booting unmodified Linux distributions is possible.||Arm DesignStart is the fastest route to designing and prototyping custom SoCs. This Research Enablement Kit demonstrates the SoC design flow and shows how to create an Arm-powered SoC using your custom IPs to validate your research effort.
More specifically, it shows how to integrate typical Floating-Point Unit (FPU) and Advanced Encryption Standard (AES) IP cores into a Cortex-M0-based SoC provided by Arm DesignStart.
|Logic IP, such as Standard Cell libraries, are the foundation for the entire backend design and optimization flow in modern application-specific integrated circuit designs. Arm has long been building high-quality logic IP with well-established optimization flows. This release offers complete, cutting-edge Arm logic IP including both front-end and back-end views, which are 1 or 2 generations newer than the logic IP freely available on DesignStart. This means that, together with Arm processor IP, you are able to explore logic IP design and optimization techniques on the latest process nodes.
|Suitable for||Computer system researchers looking to:
||Academics and researchers looking to:
||Academic researchers looking to:
|You will need||Intermediate knowledge of:
||Beginner knowledge of:
||Intermediate knowledge of: