System-on-Chip (SoC) design is mainly an integration process where designers put a set of Intellectual Property (IP) cores together using standard buses. Arm DesignStart Eval provides free of charge access to synthesizable CPU RTL and the full subsystem RTL.
This Research Enablement Kit will help you design and prototype a SoC based on the Arm Cortex-M0 CPU using the on-chip AMBA buses and the Arm DesignStart reference design.
Why use this Research Enablement Kit?
Arm DesignStart is the fastest route to designing and prototyping custom SoCs. This Research Enablement Kit demonstrates the SoC design flow and shows how to create an Arm-powered SoC using your custom IPs to validate your research effort.
More specifically, it shows how to integrate typical Floating-Point Unit (FPU) and Advanced Encryption Standard (AES) IP cores into a Cortex-M0-based SoC provided by Arm DesignStart.
The DesignStart Community facilitates discussions and provides access to technical information, whitepapers, videos, and FAQs to help you design with Arm IP.
Academics and researchers looking to:
- Integrate their custom IP core into an Arm-based SoC
- Use the exceptionally small and low power Cortex-M0 in different research areas from SoC design to IoT, parallel and heterogeneous computing
You will need:
- C: beginner knowledge
- SoC Prototyping: beginner/intermediate knowledge
- Verilog: working knowledge
SoC Design and FPGA Prototyping
- Arm DesignStart
Custom IP Integration into a Cortex-M0 based SoC
- Typical FPU IP integration
- Typical AES IP integration
You will need to download all three elements below for this Research Enablement Kit.
Please note: Arm registration is required to download Cortex-M0 DesignStart Eval.
3. Get M0 DesignStart Eval:
(Arm registration required)
Visit the DesignStart Community to find information, ask questions, get advice and connect with the experts.