Simulating a Virtual Prototype with Arm SoC Designer
Simulating a Virtual Prototype with Arm SoC Designer

Getting Started

SoC Designer simplifies virtual prototype creation. SoC Designer's easy-to-use GUI allows users to rapidly assemble models to create virtual prototypes.

Because the models are the key to creating a virtual prototype, SoC Designer supports a wide range of models in a variety of formats including:

  • Flexible SystemC model support for easy creation and integration

  • High performance cycle-accurate and implementation-accurate models compiled by Cycle Model Studio

  • Verilog and VHDL co-simulation with leading RTL Simulators

Platform Debug

Assembling system models is only part of the solution: the key lies in the ability to execute the prototype, examine the behavior of the system and analyze key metrics. SoC Designer provides debug interfaces tailored for both hardware and software engineers. You have full visibility and execution control of your design. Software engineers are able to view code, set breakpoints, and examine registers and memories. Hardware engineers can examine signals, dump waveforms, and trace execution through the system. Run-time performance profiling gives you immediate feedback on system behavior during execution.

Architectural Analysis

Development and analysis of system architecture requires the accuracy to model key system characteristics, especially with complex bus architectures and multi-core communications models. SoC Designer provides the accuracy, performance, and flexibility to model complex systems and perform the analysis required to make critical design decisions. Instead of ad-hoc model approximations and paper-and-pencil calculations, architects can now prove their design assumptions before committing to the design implementation. The unique benefits for architectural analysis enable first-turn success of your SoC:

  • Create cycle-accurate system models required for detailed architectural analysis and explore the performance impact of hardware/software trade-offs

  • Measure interconnect performance of complex bus architectures using actual system behavior to drive traffic

  • Quickly and easily make changes and explore design space alternatives before committing to an implementation

Hardware and Software System Validation

System validation requires the ability to model the entire system working together, and provide accurate models of both the hardware and software. Cycle-accurate virtual prototypes provide a way to develop and validate software before committing to physical hardware implementations. Effective driver and firmware development requires the detail and performance that is provided by SoC Designer. The benefits for hardware/software system validation provide insight:

  • Speed system integration time by debugging your software on virtual platforms before physical prototypes are available

  • Reduce risk by validating hardware implementations using actual system software

  • Eliminate hardware physical prototype availability as a bottleneck to software development

  • Accelerate the process of debugging, implementing hardware or software changes, and then re-executing the system.

Accurate Models from Arm IP Exchange

SoC Designer leverages models from Arm IP Exchange. This web portal enables around the clock access to Arm IP. Models can be easily configured, built, downloaded and managed and then dropped directly onto the SoC Designer canvas. The benefits of Arm IP Exchange are numerous:

  • Configuration — IP Exchange understands the valid configuration options for each piece of Arm IP and only permits legal combinations of these options to be chosen. 

  • Quality — Models are generated in a "clean" environment that is proven and continually regression tested. Arm IP Exchange understands the dependencies between the model and SoC Designer to ensure compatibility.

  • Usability — Models are configured using a short series of questions which automatically adapt as answers are given to ensure that only valid configurations are built. No RTL or design knowledge is required to configure or build a model.

  • Enhanced Satisfaction — Arm IP Exchange is available 24/7 allowing users to configure the model as they need it and when they need it. Users can easily check on the status of any given model they have requested to be automatically built.

  • IP Management — Arm IP Exchange maintains a secure history of user models and will automatically issue a notification as soon as a new revision or model is available. This same secure history mechanism enables users to leverage IP and configurations used elsewhere within their organization.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

SoC Designer Datasheet

Download the datasheet for ARM SoC Designer to learn more about the product.

Community Blogs

Community Forums

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0 votes 166 views 3 replies Latest 17 hours ago by vstehle Answer this
Answered Where do I find presentations and photos from SC'18? Started 6 months ago by John Linford 0 replies 975 views
Not answered What options do I have for a GUI and an LCD? Started 9 hours ago by AmyTheBUn 0 replies 17 views
Answered Mali Offline compiler GLSL clamp performance on Mali-Gxx Latest 11 hours ago by Peter Harris 3 replies 90 views
Answered how to calculate unaligned address for APB? Latest 11 hours ago by Colin Campbell 5 replies 230 views
Not answered How to get the required FLOPs for my neural network Started 12 hours ago by fset89 0 replies 25 views
Suggested answer Relocating the Vector table in Cortex - M0 Latest 13 hours ago by 42Bastian Schick 1 replies 45 views
Not answered FVP License Started 14 hours ago by Bill M 0 replies 23 views
Answered why PSTRB signal in APB4 have four bits? Latest 15 hours ago by Colin Campbell 4 replies 1108 views
Discussion 4-kbyte boundary space Latest 15 hours ago by Colin Campbell 10 replies 9697 views
Suggested answer Timer0 do not count at the theoretical frequency Latest 15 hours ago by 42Bastian Schick 1 replies 38 views
Answered Mali Graphics Debugger Memory statistics Latest 17 hours ago by Peter Harris 3 replies 264 views
Answered Disable data prefetching in a Cortex-A53 running Android Latest 17 hours ago by vstehle 3 replies 166 views