Simulating a Virtual Prototype with Arm SoC Designer
Simulating a Virtual Prototype with Arm SoC Designer

Getting Started

SoC Designer simplifies virtual prototype creation. SoC Designer's easy-to-use GUI allows users to rapidly assemble models to create virtual prototypes.

Because the models are the key to creating a virtual prototype, SoC Designer supports a wide range of models in a variety of formats including:

  • Flexible SystemC model support for easy creation and integration

  • High performance cycle-accurate and implementation-accurate models compiled by Cycle Model Studio

  • Verilog and VHDL co-simulation with leading RTL Simulators

Platform Debug

Assembling system models is only part of the solution: the key lies in the ability to execute the prototype, examine the behavior of the system and analyze key metrics. SoC Designer provides debug interfaces tailored for both hardware and software engineers. You have full visibility and execution control of your design. Software engineers are able to view code, set breakpoints, and examine registers and memories. Hardware engineers can examine signals, dump waveforms, and trace execution through the system. Run-time performance profiling gives you immediate feedback on system behavior during execution.

Architectural Analysis

Development and analysis of system architecture requires the accuracy to model key system characteristics, especially with complex bus architectures and multi-core communications models. SoC Designer provides the accuracy, performance, and flexibility to model complex systems and perform the analysis required to make critical design decisions. Instead of ad-hoc model approximations and paper-and-pencil calculations, architects can now prove their design assumptions before committing to the design implementation. The unique benefits for architectural analysis enable first-turn success of your SoC:

  • Create cycle-accurate system models required for detailed architectural analysis and explore the performance impact of hardware/software trade-offs

  • Measure interconnect performance of complex bus architectures using actual system behavior to drive traffic

  • Quickly and easily make changes and explore design space alternatives before committing to an implementation

Hardware and Software System Validation

System validation requires the ability to model the entire system working together, and provide accurate models of both the hardware and software. Cycle-accurate virtual prototypes provide a way to develop and validate software before committing to physical hardware implementations. Effective driver and firmware development requires the detail and performance that is provided by SoC Designer. The benefits for hardware/software system validation provide insight:

  • Speed system integration time by debugging your software on virtual platforms before physical prototypes are available

  • Reduce risk by validating hardware implementations using actual system software

  • Eliminate hardware physical prototype availability as a bottleneck to software development

  • Accelerate the process of debugging, implementing hardware or software changes, and then re-executing the system.

Accurate Models from Arm IP Exchange

SoC Designer leverages models from Arm IP Exchange. This web portal enables around the clock access to Arm IP. Models can be easily configured, built, downloaded and managed and then dropped directly onto the SoC Designer canvas. The benefits of Arm IP Exchange are numerous:

  • Configuration — IP Exchange understands the valid configuration options for each piece of Arm IP and only permits legal combinations of these options to be chosen. 

  • Quality — Models are generated in a "clean" environment that is proven and continually regression tested. Arm IP Exchange understands the dependencies between the model and SoC Designer to ensure compatibility.

  • Usability — Models are configured using a short series of questions which automatically adapt as answers are given to ensure that only valid configurations are built. No RTL or design knowledge is required to configure or build a model.

  • Enhanced Satisfaction — Arm IP Exchange is available 24/7 allowing users to configure the model as they need it and when they need it. Users can easily check on the status of any given model they have requested to be automatically built.

  • IP Management — Arm IP Exchange maintains a secure history of user models and will automatically issue a notification as soon as a new revision or model is available. This same secure history mechanism enables users to leverage IP and configurations used elsewhere within their organization.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

SoC Designer Datasheet

Download the datasheet for ARM SoC Designer to learn more about the product.

Community Forums

Answered Where do I find presentations and photos from SC'18? 1 votes 805 views 0 replies Started 4 months ago by John Linford Answer this
Not answered Breakpoints (S/H) could not be invoked when EL2 return EL1 0 votes 14 views 0 replies Started 6 hours ago by freshmen Answer this
Suggested answer Non-secure code calling secure code - Boot Loaders 0 votes 74 views 2 replies Latest 8 hours ago by vinkot Answer this
Suggested answer Count Main TLB miss
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0 votes 30 views 1 replies Latest yesterday by Vanhealsing Answer this
Answered is there a x86 linux distribution for cross compilation for Raspberry Pi?
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  • x86
  • Linux
0 votes 311 views 3 replies Latest yesterday by Przemyslaw Wirkus Answer this
Suggested answer Startup file uvision v5.26
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Suggested answer in debug mode, won't enter main()
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0 votes 98 views 1 replies Latest yesterday by ctarakci Answer this
Suggested answer Hi, I need RVCT V3.1 569 Any idea how / where can I get it?
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0 votes 58 views 1 replies Latest yesterday by Ronan Synnott Answer this
Discussion ds-5 提示无法连接到 fvp model是怎么回事? 0 votes 21 views 0 replies Started yesterday by kefuya Answer this
Not answered Arm RTOS C++
  • Real Time Operating Systems (RTOS)
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0 votes 47 views 0 replies Started 2 days ago by Rocketman46 Answer this
Suggested answer SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+
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0 votes 81 views 1 replies Latest 2 days ago by 42Bastian Schick Answer this
Suggested answer Interrupts in assembly language
  • Microcontroller
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0 votes 92 views 1 replies Latest 2 days ago by 42Bastian Schick Answer this
Answered Where do I find presentations and photos from SC'18? Started 4 months ago by John Linford 0 replies 805 views
Not answered Breakpoints (S/H) could not be invoked when EL2 return EL1 Started 6 hours ago by freshmen 0 replies 14 views
Suggested answer Non-secure code calling secure code - Boot Loaders Latest 8 hours ago by vinkot 2 replies 74 views
Suggested answer Count Main TLB miss Latest yesterday by Vanhealsing 1 replies 30 views
Answered is there a x86 linux distribution for cross compilation for Raspberry Pi? Latest yesterday by Przemyslaw Wirkus 3 replies 311 views
Suggested answer Startup file uvision v5.26 Latest yesterday by ctarakci 2 replies 122 views
Suggested answer in debug mode, won't enter main() Latest yesterday by ctarakci 1 replies 98 views
Suggested answer Hi, I need RVCT V3.1 569 Any idea how / where can I get it? Latest yesterday by Ronan Synnott 1 replies 58 views
Discussion ds-5 提示无法连接到 fvp model是怎么回事? Started yesterday by kefuya 0 replies 21 views
Not answered Arm RTOS C++ Started 2 days ago by Rocketman46 0 replies 47 views
Suggested answer SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+ Latest 2 days ago by 42Bastian Schick 1 replies 81 views
Suggested answer Interrupts in assembly language Latest 2 days ago by 42Bastian Schick 1 replies 92 views