Introducing the next generation of AXI and ACE protocols

Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols have been implemented in Arm’s latest technology including DynamIQ processers such as Cortex-A75 and Cortex-A55 along with the CoreLink CMN-600 Coherent Mesh Network. 

To recap, here are the 3 main protocols included within the ACE and AXI specification:

• AXI (Advance Extensible Interface) – AXI provides connectivity for non-coherent masters and slaves
• ACE (AXI Coherency Extensions) – Supports full coherency for masters with caches such as Cortex-A processors.
• ACE-Lite – Supports IO coherency for masters without caches (Accelerators, IO, etc) that share coherent memory space.

As mentioned, the new AMBA 5 ACE5, ACE5-Lite and AXI5 align with CHI to provide a number of performance and reliability capabilities including Atomics, Cache Stashing and RAS signaling. The table below provides a high-level overview of which enhancements are available for the different protocols and the following CHI release blog post describes the features and benefits in more depth.

Introducing new AMBA 5 CHI protocol enhancements | Specification now available blog post

Enhancements	CHI	AXI5	ACE5-Lite	ACE5
ARMv8.1-A DVM	X	X	X	X
CMO for persistence	X	X	X	X
RAS signaling	X	X	X	X
IO De-allocation	X	X	X	X
Trace tag	X	X	X	X
Atomics	X	X	X
Cache stashing	X	X	X
Direct data return	X
QoS_Accept		X	X	X

To find out more details about the new protocols, please see the specification which is now available for download on the Arm Developer AMBA 5 website. 

AMBA 5