- To configure the CCN-504 on Arm IP Exchange, select the desired interface types, node population, and other hardware details and click the "Build It" button to compile a model.
Defining the Memory Map
One of the challenges of configuring CHI systems is to make sure the System Address Map (SAM) is correctly defined. As indicated in the table above, the process is more complex compared to a simple memory map with address ranges assigned to ports.
The network layer of the protocol is responsible for routing packets between nodes. CHI is a layered protocol consisting of nodes of various types. Each node has a unique Network ID and each packet specifies a Target ID to send the packet to and a Source ID to be able to route the response.
For a system with A57 CPUs and a CCN-504 each Request Node (RN), such as a CPU, has a System Address Map (SAM) which is used to determine where to send packets. There are three possible node types a message could be sent to:
- Miscellaneous Node (MN)
- Home Node I/O coherent (HN-I)
- Home Node Fully coherent (HN-F)
DVM and Barrier messages are always sent to the MN so the challenge is to determine which of the possible Home Nodes an address is destined for. The make the calculation of which HN-F is targeted the RN uses an address hash function. This can be found in the CCN-504 TRM.
Each CCN has a different hashing function depending on how many HN-F partitions are being used. The hashing function calculates the HN-F to be used, but this is still not a Network ID. Additional configuration signals provide the mapping from HN-F number to Node ID.
This means there are a number of SAM* parameters for the Cortex-A57 and the CCN-504 which must be set correctly for the memory map to function. It also means that a debugging tool which makes use of back-door memory access needs to understand the hashing function to know where to find the correct data for a given address. SoC Designer takes all of this into consideration to provide system debugging.
Cycle Models use configuration parameters to perform the following tasks:
- Associate each address region with HN-Fs or HN-Is
- Specify the Node ID values of Home Nodes and the Miscellaneous Node
- Define the number of Home Nodes
- Specify the Home Nodes as Fully Coherent or I/O Coherent
The parameters for the Cortex-A57 CPU model are shown below:
The parameters for the CCN-504 model are similar, a list of SAMADDRMAP* values and SAM*NODEID values. It is important to ensure the parameters are correctly set for the system to function properly.
The CCN System
Sometimes it’s helpful to have a picture of all of the parts of a CCN system. The graphic below provides an overview to all parts of a CCN system, and can help engineers to keep track of the node types and node id values in a system.
SoC Designer Features
With the introduction of AMBA 5 CHI, SoC Designer has been enhanced to provide CHI breakpoints, monitors, and profiling information.
Screenshots of CHI transactions and CHI profiling are shown below. The Target ID and the Source ID for each transaction are shown. This is from the single-core Cortex-A57 CPAK so the SourceID values are always 1. Multi-core CPAKs will create transactions with different SourceID values.
The CCN-504 has a large number of PMU events which can be used to understand performance.
AMBA 5 CHI is targeted at systems with larger numbers of coherent masters and its system memory map is more complex compared to ACE systems. A number of System Address Map parameters are required to build a working system, both for the CPU and for the interconnect.
SoC Designer enables users to experiment and learn how CHI systems work, while pre-configured CPAKs are available on Arm System Exchange which demonstrate hardware configuration as well as the software programming needed to initialize a CHI system. Just like the address map, the initialization software is more complex compared to an ACE system with a CCI-400 or CCI-500.